Semiconductor & Computer Engineering
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Difference between revisions of "10 µm lithography process"
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== 10 µm Chips == | == 10 µm Chips == | ||
* Intel | * Intel | ||
Revision as of 15:17, 21 August 2016
Semiconductor lithography processes technology
The 10 µm lithography process was the semiconductor process technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process at companies such as Fairchild and TI were 1.5 inch (38 mm).
Industry
| Fab |
|---|
| Process Name |
| 1st Production |
| Contacted Gate Pitch |
| Interconnect Pitch |
| Metal Layers |
| Technology |
| Wafer |
| Intel | TI | RCA | Fairchild | National | MIL |
|---|---|---|---|---|---|
| 1970 | 1969 | 1969 | 1969 | ||
| ? nm | ? nm | ? nm | ? nm | ? nm | ? nm |
| ? nm | ? nm | ? nm | ? nm | ? nm | ? nm |
| 2 | 2 | 2 | 2 | ||
| PMOS | PMOS | CMOS | PMOS | PMOS | |
| 51 mm |
10 µm Microprocessors
This list is incomplete; you can help by expanding it.
Click to browse all 10 µm models
10 µm Chips
- Intel
- RCA
This list is incomplete; you can help by expanding it.
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