Semiconductor & Computer Engineering
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Difference between revisions of "40 nm lithography process"
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| 162 nm || 1.01x || 129 nm || 0.65x || 168 nm || 0.67x || 140 nm || ?x | | 162 nm || 1.01x || 129 nm || 0.65x || 168 nm || 0.67x || 140 nm || ?x | ||
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| − | | | + | | 120 nm || ?x || 117 nm || 0.65x || ? nm || ?x || ? nm || ?x |
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| 0.242 µm<sup>2</sup> || 0.46x || ? µm<sup>2</sup> || ?x || 0.195 µm<sup>2</sup> || 0.33x || 0.250 µm<sup>2</sup> || ?x | | 0.242 µm<sup>2</sup> || 0.46x || ? µm<sup>2</sup> || ?x || 0.195 µm<sup>2</sup> || 0.33x || 0.250 µm<sup>2</sup> || ?x | ||
Revision as of 10:16, 25 April 2016
Semiconductor lithography processes technology
The 40 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 45 nm and 32 nm processes. Commercial integrated circuit manufacturing using 40 nm process began in 2008 by leading semiconductor companies such as TSMC. This technology superseded by commercial 32 nm process by 2010.
Industry
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| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell |
| TSMC | Samsung | Toshiba / NEC | Crolles2 Alliance | ||||
|---|---|---|---|---|---|---|---|
| Value | 65 nm Δ | Value | 65 nm Δ | Value | 65 nm Δ | Value | 65 nm Δ |
| 162 nm | 1.01x | 129 nm | 0.65x | 168 nm | 0.67x | 140 nm | ?x |
| 120 nm | ?x | 117 nm | 0.65x | ? nm | ?x | ? nm | ?x |
| 0.242 µm2 | 0.46x | ? µm2 | ?x | 0.195 µm2 | 0.33x | 0.250 µm2 | ?x |
40 nm Microprocessors
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40 nm System on Chips
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