Semiconductor & Computer Engineering
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Difference between revisions of "20 nm lithography process"
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| − | ! colspan="2" | [[Samsung]] | + | ! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] |
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| − | ! Value !! [[28 nm]] Δ | + | ! Value !! [[28 nm]] Δ !! Value !! [[28 nm]] Δ |
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| − | | 64 nm || 0.71x | + | | 64 nm || 0.71x || 87 nm || 0.71x |
|- | |- | ||
| − | | 64 nm || 0.67x | + | | 64 nm || 0.67x || 67 nm || 0.70x |
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| − | | ? µm<sup>2</sup> || ?x | + | | ? µm<sup>2</sup> || ?x || 0.07 µm<sup>2</sup> || 0.45x |
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Revision as of 04:30, 24 April 2016
Semiconductor lithography processes technology
The 20 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 22 nm and 16 nm processes. Commercial integrated circuit manufacturing using 20 nm process began in 2014. This technology superseded by commercial 16 nm process.
Industry
| Fab |
|---|
| |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell |
| Samsung | TSMC | ||
|---|---|---|---|
| Value | 28 nm Δ | Value | 28 nm Δ |
| 64 nm | 0.71x | 87 nm | 0.71x |
| 64 nm | 0.67x | 67 nm | 0.70x |
| ? µm2 | ?x | 0.07 µm2 | 0.45x |
20 nm Microprocessors
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20 nm System on Chips
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20 nm Microarchitectures
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