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Difference between revisions of "130 nm lithography process"

(Industry)
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! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[IBM]]
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! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[IBM]]
 
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| colspan="6" | Bulk || colspan="2" | PDSOI
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| colspan="8" | Bulk || colspan="2" | PDSOI
 
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! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ
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! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ
 
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| 319 nm || 0.66x || 310 nm || ?x || 350 nm || ?x || 350 nm || ?x
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| 319 nm || 0.66x || 310 nm || ?x || 350 nm || ?x || ? nm || ?x || 350 nm || ?x
 
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| 345 nm || 0.69x || 340 nm || ?x || 350 nm || ?x || ? nm || ?x
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| 345 nm || 0.69x || 340 nm || ?x || 350 nm || ?x || ? nm || ?x || ? nm || ?x
 
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| 2.0 µm<sup>2</sup> || 0.36x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || 1.8 µm<sup>2</sup> || ?x
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| 2.0 µm<sup>2</sup> || 0.36x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || 1.98 µm<sup>2</sup> || 0.47x || 1.8 µm<sup>2</sup> || ?x
 
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=== Design Rules ===
 
=== Design Rules ===

Revision as of 03:10, 24 April 2016

The 130 nm lithography process is a full node semiconductor manufacturing process following the 150 nm process stopgap. Commercial integrated circuit manufacturing using 130 nm process began in 2001. This technology was replaced by with 110 nm process (HN) in 2003 and 90 nm process (FN) in 2004.

Industry

Fab
Type​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Intel TSMC Samsung Fujitsu IBM
Bulk PDSOI
Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ
319 nm 0.66x 310 nm  ?x 350 nm  ?x  ? nm  ?x 350 nm  ?x
345 nm 0.69x 340 nm  ?x 350 nm  ?x  ? nm  ?x  ? nm  ?x
2.0 µm2 0.36x  ? µm2  ?x  ? µm2  ?x 1.98 µm2 0.47x 1.8 µm2  ?x

Design Rules

130 nm Microprocessors

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130 nm System on Chips

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130 nm Microarchitectures

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