Difference between revisions of "22 nm lithography process"

Revision as of 01:31, 24 April 2016

Semiconductor lithography processes technology

The 22 nm lithography process is a full node semiconductor manufacturing process following the 28 nm process stopgap. Commercial integrated circuit manufacturing using 22 nm process began in 2008 for memory and 2012 for MPUs. This technology was replaced by with 20 nm process (HN) in 2014 and 16 nm process (FN) in late 2015.

Industry

The 22 nm became Intel's first generation of Tri-gate FinFET transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. Those transistors were not used in IBM's process

Fab

Fin Pitch
Fin Width
Fin Height
Contacted Gate Pitch
Interconnect Pitch (M1P)
SRAM bit cell (HP)
SRAM bit cell (HD)

Intel		Common Platform
Value	32 nm Δ	Value	32 nm Δ
60 nm	N/A
32 nm
8 nm
90 nm	0.80x	100 nm	0.79x
80 nm	0.71x	80 nm	?x
0.1080 µm²	0.63x	0.1 µm²	?x
0.092 µm²	?x

Design Rules

SoC Interconnect Design Rules
Layer	Pitch	Process	Dielectric Materials	CPU	SoC
Fin	60 nm	-	-	Fin	Fin
Contact	90 nm	SAC	-	Contact	Contact
M1	90 nm	SAV	ULK CDO	M1	M1
MT - 1x	80 nm	SAV	ULK CDO	M2/M3	2-6 layers
MT - 1.4x	112 nm	SAV	ULK CDO	M4	Semi-global
MT - 2x	160 nm	SAV	ULK CDO	M5	Semi-global
MT - 3x	240 nm	SAV	ULK CDO	M6	Global Routing
MT - 4x	320 nm 360 nm	Via First	LK CDO	M7/M8	Global Routing
MT - TOP	14 µm	Plate Up	Polymer	M9	Top Metal

22 nm Microprocessors

Intel
- Core i7EE

This list is incomplete; you can help by expanding it.

22 nm System on Chips

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22 nm Microarchitectures

Intel:

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@@ Line 3: / Line 3: @@
 == Industry ==
+The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. Those transistors were not used in IBM's process
-=== Intel ===
+{{scrolling table/top|style=text-align: right; | first=Fab
-nm was Intel's first generation of Tri-gate [[FinFET]] transistors.
+ |&nbsp;
-{| class="wikitable"
+ |Fin Pitch
+ |Fin Width
+ |Fin Height
+ |Contacted Gate Pitch
+ |Interconnect Pitch (M1P)
+ |SRAM bit cell (HP)
+ |SRAM bit cell (HD)
+}}
+{{scrolling table/mid}}
 |-
-| || Measurement || Scaling from [[32 nm]]
+! colspan="2" | [[Intel]] !! colspan="2" | Common Platform
 |-
-| Fin Pitch || 60 nm ||
+! Value !! [[32 nm]] Δ !! Value !! [[32 nm]] Δ
 |-
-| Contacted Gate Pitch || 90 nm || 0.80x
+| 60 nm || colspan="3" rowspan="3" style="text-align: center;" | N/A
 |-
-| Interconnect Pitch (M1P) || 80 nm || 0.71x
+| 32 nm
 |-
-| [[SRAM]] bit cell || 0.1080 µm<sup>2</sup> || High Performance
+| 8 nm
+|-
+| 90 nm || 0.80x || 100 nm || 0.79x
+|-
+| 80 nm || 0.71x || 80 nm || ?x
+|-
+| 0.1080 µm<sup>2</sup> || 0.63x || 0.1 µm<sup>2</sup>  || ?x
+|-
+| 0.092 µm<sup>2</sup> || ?x
+{{scrolling table/end}}
+=== Design Rules ===
+{| class="wikitable collapsible collapsed"
 |-
-| [[SRAM]] bit cell || 0.092 µm<sup>2</sup> || High Density
-|}
-{| class="wikitable"
 ! colspan="6" | SoC Interconnect Design Rules
 |-
@@ Line 43: / Line 59: @@
 |-
 | MT - TOP || 14 µm || Plate Up || Polymer || M9 || Top Metal
-|}
-=== IBM ===
-{| class="wikitable"
-|-
-| || Measurement
-|-
-| Contacted Gate Pitch || 100 nm
-|-
-| Interconnect Pitch (M1P) || 80 nm
-|-
-| [[SRAM]] bit cell || ? µm<sup>2</sup>
 |}

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Revision as of 01:31, 24 April 2016

Contents

Industry

Design Rules

22 nm Microprocessors

22 nm System on Chips

22 nm Microarchitectures