Semiconductor & Computer Engineering
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| process 2 dram = | | process 2 dram = | ||
| process 2 dram Δ = | | process 2 dram Δ = | ||
| + | <!-- GlobalFoundries --> | ||
| + | | process 3 fab = [[GlobalFoundries]] | ||
| + | | process 3 name = | ||
| + | | process 3 date = | ||
| + | | process 3 lith = EUV | ||
| + | | process 3 immersion = | ||
| + | | process 3 exposure = SE | ||
| + | | process 3 wafer type = Bulk | ||
| + | | process 3 wafer size = 300 nm | ||
| + | | process 3 transistor = | ||
| + | | process 3 volt = | ||
| + | | process 3 delta from = [[5 nm]] Δ | ||
| + | | process 3 fin pitch = | ||
| + | | process 3 fin pitch Δ = | ||
| + | | process 3 fin width = | ||
| + | | process 3 fin width Δ = | ||
| + | | process 3 fin height = | ||
| + | | process 3 fin height Δ = | ||
| + | | process 3 gate len = | ||
| + | | process 3 gate len Δ = | ||
| + | | process 3 cpp = | ||
| + | | process 3 cpp Δ = | ||
| + | | process 3 mmp = | ||
| + | | process 3 mmp Δ = | ||
| + | | process 3 sram hp = | ||
| + | | process 3 sram hp Δ = | ||
| + | | process 3 sram hd = | ||
| + | | process 3 sram hd Δ = | ||
| + | | process 3 sram lv = | ||
| + | | process 3 sram lv Δ = | ||
| + | | process 3 dram = | ||
| + | | process 3 dram Δ = | ||
<!-- Samsung --> | <!-- Samsung --> | ||
| process 4 fab = [[Samsung]] | | process 4 fab = [[Samsung]] | ||
Revision as of 08:15, 18 April 2019
Semiconductor lithography processes technology
The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin sometimes around 2023.
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.
Industry
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Intel | TSMC | GlobalFoundries | Samsung | ||||
|---|---|---|---|---|---|---|---|
| P1280? (CPU), P1281? (SoC) | 3LLP 3nm Low Power Plus
| ||||||
| EUV | EUV | EUV | EUV | ||||
| SE | SE | SE | SE | ||||
| Bulk | Bulk | Bulk | Bulk | ||||
| 300 nm | 300 nm | 300 nm | 300 nm | ||||
| GAA | |||||||
| Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ |
| N/A | |||||||
Samsung
On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.
3 nm Microprocessors
This list is incomplete; you can help by expanding it.
3 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017