Semiconductor & Computer Engineering
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Difference between revisions of "14 nm lithography process"
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| process 2 name = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> | | process 2 name = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> | ||
| process 2 date = 2015 | | process 2 date = 2015 | ||
| − | | process 2 lith = | + | | process 2 lith = 193 nm |
| process 2 immersion = | | process 2 immersion = | ||
| process 2 exposure = | | process 2 exposure = | ||
| Line 74: | Line 74: | ||
| process 3 name = | | process 3 name = | ||
| process 3 date = | | process 3 date = | ||
| − | | process 3 lith = | + | | process 3 lith = 193 nm |
| process 3 immersion = | | process 3 immersion = | ||
| process 3 exposure = | | process 3 exposure = | ||
| Line 106: | Line 106: | ||
| process 4 name = | | process 4 name = | ||
| process 4 date = | | process 4 date = | ||
| − | | process 4 lith = | + | | process 4 lith = 193 nm |
| process 4 immersion = | | process 4 immersion = | ||
| process 4 exposure = | | process 4 exposure = | ||
| Line 134: | Line 134: | ||
| process 4 dram = | | process 4 dram = | ||
| process 4 dram Δ = | | process 4 dram Δ = | ||
| + | <!-- UMC --> | ||
| + | | process 5 fab = [[Common Platform Alliance]]<info>The '''Common Platform Alliance''' is a joint collaboration between [[IBM]], [[STMicroelectronics]]</info> | ||
| + | | process 5 name = 14FDSOI | ||
| + | | process 5 date = | ||
| + | | process 5 lith = 193 nm | ||
| + | | process 5 immersion = Yes | ||
| + | | process 5 exposure = DP | ||
| + | | process 5 wafer type = SOI | ||
| + | | process 5 wafer size = 300 mm | ||
| + | | process 5 transistor = Planar | ||
| + | | process 5 volt = 0.8 V | ||
| + | | process 5 delta from = [[28 nm]] Δ | ||
| + | | process 5 fin pitch = - | ||
| + | | process 5 fin pitch Δ = | ||
| + | | process 5 fin width = | ||
| + | | process 5 fin width Δ = | ||
| + | | process 5 fin height = | ||
| + | | process 5 fin height Δ = | ||
| + | | process 5 gate len = 20 nm | ||
| + | | process 5 gate len Δ = 0.71x | ||
| + | | process 5 cpp = 90 nm | ||
| + | | process 5 cpp Δ = 0.79x | ||
| + | | process 5 mmp = 64 nm | ||
| + | | process 5 mmp Δ = 0.71x | ||
| + | | process 5 sram hp = 0.090 µm² | ||
| + | | process 5 sram hp Δ = 0.59x | ||
| + | | process 5 sram hd = 0.081 µm² | ||
| + | | process 5 sram hd Δ = 0.68x | ||
| + | | process 5 sram lv = | ||
| + | | process 5 sram lv Δ = | ||
| + | | process 5 dram = | ||
| + | | process 5 dram Δ = | ||
}} | }} | ||
=== Intel === | === Intel === | ||
| Line 214: | Line 246: | ||
* Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015. | * Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015. | ||
* Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 158-169. | * Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 158-169. | ||
| + | * Weber, Olivier, et al. "14nm FDSOI technology for high speed and energy efficient applications." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014. | ||
| + | |||
[[Category:Lithography]] | [[Category:Lithography]] | ||
Revision as of 21:21, 6 April 2017
Semiconductor lithography processes technology
The 14 nanometer (14 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 16 nm and 10 nm processes. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 14 nm process began in 2014. This technology is set to be replaced with 10 nm process in 2017.
Contents
Industry
14 nm became Intel's 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Intel makes use of Self-Aligned Double Patterning (SADP) with 193 nm immersion lithography at critical patterning layers.
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Intel | Samsung Alliance Samsung Alliance consists of a process development collaboration between Samsung and GlobalFoundries. GlobalFoundries licenses Samsung's 14nm process at Fab8, New York. |
IBM | UMC | Common Platform Alliance The Common Platform Alliance is a joint collaboration between IBM, STMicroelectronics
| |||||
|---|---|---|---|---|---|---|---|---|---|
| P1272 (CPU) / P1273 (SoC) | 14LPE 1st generation; 14 nm Low Power Early , 14LPP2nd generation; 14 nm Low Power Performance , 14LPC3rd generation; 14 nm Low Power Cost [reduced] , 14LPU4th generation; 14 nm Low Power Ultimate |
14FDSOI | |||||||
| 2014 | 2015 | ||||||||
| 193 nm | 193 nm | 193 nm | 193 nm | 193 nm | |||||
| Yes | Yes | ||||||||
| DP | |||||||||
| Bulk | Bulk | SOI | SOI | ||||||
| 300 mm | 300 mm | 300 mm | 300 mm | 300 mm | |||||
| FinFET | FinFET | FinFET | FinFET | Planar | |||||
| 0.7 V | 0.7 V | 0.8 V | |||||||
| Value | 22 nm Δ | Value | 20 nm Δ | Value | 22 nm Δ | Value | 28 nm Δ | Value | 28 nm Δ |
| 42 nm | 0.70x | 48 nm | N/A | 42 nm | N/A | N/A | |||
| 8 nm | 1.00x | 8 nm | 10 nm | ||||||
| 42 nm | 1.24x | ~38 nm | 25 nm | ||||||
| 20 nm | 0.77x | 30 nm | 20 nm | 0.71x | |||||
| 70 nm | 0.78x | 78 nm | 1.22x | 80 nm | 0.80x | 90 nm | 0.79x | ||
| 52 nm | 0.65x | 64 nm | 1.00x | 64 nm | 0.80x | 64 nm | 0.71x | ||
| 0.0706 µm² | 0.54x | 0.080 µm² | 0.78x | 0.0900 µm² | 0.63x | 0.090 µm² | 0.59x | ||
| 0.0499 µm² | 0.54x | 0.064 µm² | 0.79x | 0.0810 µm² | 0.81x | 0.081 µm² | 0.68x | ||
| 0.0588 µm² | 0.54x | ||||||||
| 0.0174 µm² | 0.67x | ||||||||
Intel
| Intel 14nm Design Rules | ||
|---|---|---|
| Layer | Pitch | Scale Factor |
| Fin | 42 nm | 0.70 |
| Contacted Gate Pitch | 70 nm | 0.78 |
| Metal 0 | 56 | - |
| Metal 1 | 70 | 0.78 |
| Metal 2 | 52 | 0.65 |
Find models
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14 nm Microprocessors
- Intel
- AMD
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14 nm Microarchitectures
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Documents
References
- Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
- Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
- Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015.
- Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 158-169.
- Weber, Olivier, et al. "14nm FDSOI technology for high speed and energy efficient applications." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.