Semiconductor & Computer Engineering
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Difference between revisions of "14 nm lithography process"
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| Line 50: | Line 50: | ||
| process 2 volt = | | process 2 volt = | ||
| process 2 delta from = [[20 nm]] Δ | | process 2 delta from = [[20 nm]] Δ | ||
| − | | process 2 fin pitch = | + | | process 2 fin pitch = 48 nm |
| − | | process 2 fin pitch Δ = | + | | process 2 fin pitch Δ = - |
| − | | process 2 fin width = | + | | process 2 fin width = 8 nm |
| process 2 fin width Δ = | | process 2 fin width Δ = | ||
| − | | process 2 fin height = | + | | process 2 fin height = ~38 nm |
| process 2 fin height Δ = | | process 2 fin height Δ = | ||
| − | | process 2 gate len = | + | | process 2 gate len = 30 nm |
| process 2 gate len Δ = | | process 2 gate len Δ = | ||
| − | | process 2 cpp = | + | | process 2 cpp = 78 nm |
| − | | process 2 cpp Δ = | + | | process 2 cpp Δ = 1.22x |
| − | | process 2 mmp = | + | | process 2 mmp = 64 nm |
| − | | process 2 mmp Δ = | + | | process 2 mmp Δ = 1.00x |
| − | | process 2 sram hp = | + | | process 2 sram hp = 0.0806 µm² |
| process 2 sram hp Δ = | | process 2 sram hp Δ = | ||
| − | | process 2 sram hd = | + | | process 2 sram hd = 0.064 µm² |
| process 2 sram hd Δ = | | process 2 sram hd Δ = | ||
| process 2 sram lv = | | process 2 sram lv = | ||
| Line 82: | Line 82: | ||
| process 3 volt = | | process 3 volt = | ||
| process 3 delta from = [[20 nm]] Δ | | process 3 delta from = [[20 nm]] Δ | ||
| − | | process 3 fin pitch = | + | | process 3 fin pitch = 48 nm |
| − | | process 3 fin pitch Δ = | + | | process 3 fin pitch Δ = - |
| − | | process 3 fin width = | + | | process 3 fin width = 8 nm |
| process 3 fin width Δ = | | process 3 fin width Δ = | ||
| − | | process 3 fin height = | + | | process 3 fin height = ~38 nm |
| process 3 fin height Δ = | | process 3 fin height Δ = | ||
| − | | process 3 gate len = | + | | process 3 gate len = 30 nm |
| process 3 gate len Δ = | | process 3 gate len Δ = | ||
| − | | process 3 cpp = | + | | process 3 cpp = 78 nm |
| − | | process 3 cpp Δ = | + | | process 3 cpp Δ = 1.22x |
| − | | process 3 mmp = | + | | process 3 mmp = 64 nm |
| − | | process 3 mmp Δ = | + | | process 3 mmp Δ = 1.00x |
| − | | process 3 sram hp = | + | | process 3 sram hp = 0.0806 µm² |
| process 3 sram hp Δ = | | process 3 sram hp Δ = | ||
| − | | process 3 sram hd = | + | | process 3 sram hd = 0.064 µm² |
| process 3 sram hd Δ = | | process 3 sram hd Δ = | ||
| process 3 sram lv = | | process 3 sram lv = | ||
| Line 114: | Line 114: | ||
| process 4 volt = | | process 4 volt = | ||
| process 4 delta from = [[22 nm]] Δ | | process 4 delta from = [[22 nm]] Δ | ||
| − | | process 4 fin pitch = | + | | process 4 fin pitch = 42 nm |
| − | | process 4 fin pitch Δ = | + | | process 4 fin pitch Δ = - |
| − | | process 4 fin width = | + | | process 4 fin width = 10 nm |
| process 4 fin width Δ = | | process 4 fin width Δ = | ||
| − | | process 4 fin height = | + | | process 4 fin height = 25 nm |
| process 4 fin height Δ = | | process 4 fin height Δ = | ||
| process 4 gate len = | | process 4 gate len = | ||
| process 4 gate len Δ = | | process 4 gate len Δ = | ||
| − | | process 4 cpp = | + | | process 4 cpp = 80 nm |
| − | | process 4 cpp Δ = | + | | process 4 cpp Δ = 0.80x |
| − | | process 4 mmp = | + | | process 4 mmp = 64 nm |
| − | | process 4 mmp Δ = | + | | process 4 mmp Δ = 0.80x |
| − | | process 4 sram hp = | + | | process 4 sram hp = 0.900 µm² |
| process 4 sram hp Δ = | | process 4 sram hp Δ = | ||
| − | | process 4 sram hd = | + | | process 4 sram hd = 0.081 µm² |
| − | | process 4 sram hd Δ = | + | | process 4 sram hd Δ = 0.81x |
| process 4 sram lv = | | process 4 sram lv = | ||
| process 4 sram lv Δ = | | process 4 sram lv Δ = | ||
| − | | process 4 dram = | + | | process 4 dram = 0.0174 µm² |
| − | | process 4 dram Δ = | + | | process 4 dram Δ = 0.67x |
<!-- UMC --> | <!-- UMC --> | ||
| process 5 fab = [[UMC]] | | process 5 fab = [[UMC]] | ||
| Line 244: | Line 244: | ||
* Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. | * Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. | ||
* Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. | * Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. | ||
| + | * Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015. | ||
[[Category:Lithography]] | [[Category:Lithography]] | ||
Revision as of 03:42, 5 April 2017
Semiconductor lithography processes technology
The 14 nanometer (14 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 16 nm and 10 nm processes. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 14 nm process began in 2014. This technology is set to be replaced with 10 nm process in 2017.
Contents
Industry
14 nm became Intel's 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Intel makes use of Self-Aligned Double Patterning (SADP) with 193 nm immersion lithography at critical patterning layers.
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Intel | Samsung | GlobalFoundries | IBM | UMC | |||||
|---|---|---|---|---|---|---|---|---|---|
| P1272 (CPU) / P1273 (SoC) | 14LPE 1st generation; 14 nm Low Power Early , 14LPP2nd generation; 14 nm Low Power Performance , 14LPC3rd generation; 14 nm Low Power Cost [reduced] , 14LPU4th generation; 14 nm Low Power Ultimate |
14LPP 2nd generation; 14 nm Low Power Performance |
|||||||
| 2014 | |||||||||
| Bulk | Bulk | Bulk | SOI | ||||||
| 300 mm | 300 mm | 300 mm | 300 mm | 300 mm | |||||
| FinFET | FinFET | FinFET | FinFET | FinFET | |||||
| Value | 22 nm Δ | Value | 20 nm Δ | Value | 20 nm Δ | Value | 22 nm Δ | Value | 28 nm Δ |
| 42 nm | 0.70x | 48 nm | N/A | 48 nm | N/A | 42 nm | N/A | ||
| 8 nm | 1.00x | 8 nm | 8 nm | 10 nm | |||||
| 42 nm | 1.24x | ~38 nm | ~38 nm | 25 nm | |||||
| 20 nm | 0.77x | 30 nm | 30 nm | ||||||
| 70 nm | 0.78x | 78 nm | 1.22x | 78 nm | 1.22x | 80 nm | 0.80x | ||
| 52 nm | 0.65x | 64 nm | 1.00x | 64 nm | 1.00x | 64 nm | 0.80x | ||
| 0.0706 µm² | 0.0806 µm² | 0.0806 µm² | 0.900 µm² | ||||||
| 0.0499 µm² | 0.064 µm² | 0.064 µm² | 0.081 µm² | 0.81x | |||||
| 0.0588 µm² | |||||||||
| 0.0174 µm² | 0.67x | ||||||||
Intel
| Intel 14nm Design Rules | ||
|---|---|---|
| Layer | Pitch | Scale Factor |
| Fin | 42 nm | 0.70 |
| Contacted Gate Pitch | 70 nm | 0.78 |
| Metal 0 | 56 | - |
| Metal 1 | 70 | 0.78 |
| Metal 2 | 52 | 0.65 |
Find models
Click to browse all 14 nm MPU models
14 nm Microprocessors
- Intel
- AMD
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14 nm Microarchitectures
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Documents
References
- Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
- Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
- Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015.