Revision as of 18:29, 10 March 2017

Semiconductor lithography processes technology

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The 20 nanometer (20 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 22 nm and 16 nm processes. The term "20 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 20 nm process began in 2014. This technology superseded by commercial 16 nm process.

Industry

TSMC

TSMC demonstrated their 112 Mebibit SRAM wafer from their 20 nm HKMG process at the 2013 IEEE ISSCC.

TSMC 112 Mib SRAM demo 20 nm wafer[1]
Technology 20 nm HK-MG Metal scheme 1 Poly / 7 Metal Supply voltage 0.95 V (core) 1.8 V (i/o) Bit cell size 0.081 µm² macro configs 2048x134 MUX4 Capacity 112 Mib Test Features Row/Column Redundancy Programmable E-fuse Die Size 6400 µm x 6300 µm = 40.32 mm²

20 nm Microprocessors

• MediaTek
  • Helio

This list is incomplete; you can help by expanding it.

20 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References