Revision as of 17:13, 10 March 2017

Semiconductor lithography processes technology

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The 7 nanometer (7 nm) lithography process is a full node semiconductor manufacturing process following the 10 nm process node. The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of integrated circuit using 7 nm process is set to begin sometimes in 2019 or 2020. This technology will be replaced by 5 nm process around 2022.

Industry

In ISSCC 2017, the memory group at TSMC detailed their test 128 MiB SRAM chip which featured a 42.64 mm² die^[1]. The chip is manufactured on TSMC's 7nm HK-MG FinFET process. The chip, which initially debuted in last year's ISSCC, makes use of 0.027 µm² bit cells, currently the smallest such cells in risk production. The over die is 0.34x smaller than their 16 nm process version. At the same conference, Samsung detailed limited use for EUV in their 7nm node, though not much more is known. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process.

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

TSMC

TSMC demonstrated their 256 Mebibit SRAM wafer from their 7nm HKMG FinFET process. Their chip makes use of 34% of the area of their 16 nm process demo chip counterpart.

TSMC 256 Mib SRAM demo wafer[1]
Technology 7 nm HK-MG FinFET Metal scheme 1P7M Supply voltage 0.75 V (core) 1.8 V (i/o) Bit cell size 0.027 µm² macro configs 4096x32 MUX16 258 bits/BL 272 bits/WL Capacity 256 Mib Test Features Row/Column Redundancy Programmable E-fuse Die Size 5903 µm x 7223 µm = 42.64 mm²

7 nm Microprocessors

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7 nm Microarchitectures

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References