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Difference between revisions of "7 nm lithography process"
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| − | | ? nm || ?x || ? | + | | ? nm || ?x || 48 nm<ref>http://www.cdrinfo.com/Sections/News/Details.aspx?NewsId=49153</ref> || ?x || ? nm || ?x |
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| − | | ? nm || ?x || ? | + | | ? nm || ?x || 36 nm<ref>http://www.cdrinfo.com/Sections/News/Details.aspx?NewsId=49153</ref> || ?x || ? nm || ?x |
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| ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x | | ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x | ||
Revision as of 06:41, 15 November 2016
The 7 nanometer (7 nm) lithography process is a full node semiconductor manufacturing process following the 10 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes in 2019 or 2020. This technology will be replaced by 5 nm process around 2022.
Industry
| Fab |
|---|
| Process Name |
| 1st Production |
| |
| Fin Pitch |
| Fin Width |
| Fin Height |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HP) |
| SRAM bit cell (HD) |
| Intel | Samsung | TSMC | |||
|---|---|---|---|---|---|
| P1276 | |||||
| Value | 10 nm Δ | Value | 10 nm Δ | Value | 10 nm Δ |
| ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | 48 nm[1] | ?x | ? nm | ?x |
| ? nm | ?x | 36 nm[2] | ?x | ? nm | ?x |
| ? µm2 | ?x | ? µm2 | ?x | ? µm2 | ?x |
| ? µm2 | ?x | ? µm2 | ?x | ? µm2 | ?x |
7 nm Microprocessors
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7 nm System on Chips
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