Semiconductor & Computer Engineering
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Difference between revisions of "1.5 µm lithography process"
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| − | ! [[Intel]] || [[Intel]] || [[HP]] || [[AMD]] | + | ! [[Intel]] || [[Intel]] || [[Intel]] || [[HP]] || [[AMD]] |
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | HMOS-II || P646 (CHMOS III) || NMOS III || | + | | HMOS-II || HMOS-E || P646 (CHMOS III) || NMOS III || |
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | | + | | 1982 || 1982 || 1985 || 1981 || 1982 |
|- | |- | ||
| − | | ? nm || ? nm || 1.5 µm || | + | | ? nm || ? nm || ? nm || 1.5 µm || |
|- | |- | ||
| − | | ? nm || ? nm || 2.5 µm || | + | | ? nm || ? nm || ? nm || 2.5 µm || |
|- | |- | ||
| − | | 2 || 2 || 2 || 2 | + | | 2 || ? || 2 || 2 || 2 |
|- | |- | ||
| − | | ? µm<sup>2</sup> || ? µm<sup>2</sup> || ? µm<sup>2</sup> || | + | | ? µm<sup>2</sup> || ? µm<sup>2</sup> || ? µm<sup>2</sup> || ? µm<sup>2</sup> || ? µm<sup>2</sup> |
|- | |- | ||
| − | | 125 mm || 150 mm || || | + | | 125 mm || || 150 mm || || |
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Revision as of 16:44, 4 June 2016
Semiconductor lithography processes technology
The 1.5 µm lithography process was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. This process had an effective channel length of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by 1.3 µm, 1.2 µm, and 1 µm processes.
Industry
| Fab |
|---|
| Process Name |
| 1st Production |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| Metal Layers |
| SRAM bit cell |
| Wafer |
| Intel | Intel | Intel | HP | AMD |
|---|---|---|---|---|
| HMOS-II | HMOS-E | P646 (CHMOS III) | NMOS III | |
| 1982 | 1982 | 1985 | 1981 | 1982 |
| ? nm | ? nm | ? nm | 1.5 µm | |
| ? nm | ? nm | ? nm | 2.5 µm | |
| 2 | ? | 2 | 2 | 2 |
| ? µm2 | ? µm2 | ? µm2 | ? µm2 | ? µm2 |
| 125 mm | 150 mm |
Design Rules
| HP NMOS-III Design Rules | |
|---|---|
| Layer | Description |
| Oxide | 450 nm thick silicon dioxide 1.5 µm x 1.5 µm minimum contact area, zero overlap to polysilicon, zero overlap of first metal layer |
| M1 | 1.5 µm wide line / 1.0 µm space 0.4 ohm/square sheet resistance |
| Intemediate Oxide | 550 nm-thick silicon dioxide 1.5 µm x 2.0 µm minimum contact area, zero overlap to first metal layer 2.0 µm overlap of second metal layer to via |
| M2 | 5.0 µm wide line / 3.0 µm space 0.4 ohm/square sheet resistance |
1.5 µm Microprocessors
This list is incomplete; you can help by expanding it.