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Difference between revisions of "650 nm lithography process"
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| ? nm || ? nm || ? nm || ? nm || ? nm | | ? nm || ? nm || ? nm || ? nm || ? nm | ||
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Revision as of 15:41, 30 March 2017
Semiconductor lithography processes technology |
|
The 650 nanometer (650 nm) lithography process was a semiconductor manufacturing process used by some integrated circuit manufacturers in early 1990s. This process was later replaced by 500 nm and 350 nm processes.
Industry
Fab |
---|
Process Name |
1st Production |
|
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell |
Cypress | IDT | TI | IBM | Motorola |
---|---|---|---|---|
1992 | 1993 | 1993 | 1995 | 1995 |
Value | Value | Value | Value | Value |
? nm | ? nm | ? nm | ? nm | ? nm |
? nm | ? nm | ? nm | ? nm | ? nm |
? µm² | ? µm² | ? µm² | ? µm² | ? µm² |
650 nm Microprocessors
- Cyrix
- Cx5x86-100GP, 100 MHz, July 1995
- 486 DX
- 5x86
- IBM (also made by Motorola)
- PowerPC 601, 110 MHz / 120 MHz
- Motorola
- Ross