Semiconductor & Computer Engineering
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Difference between revisions of "28 nm lithography process"
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! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[STMicroelectronics]] !! colspan="2" | [[UMC]] | ! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[STMicroelectronics]] !! colspan="2" | [[UMC]] | ||
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| + | | colspan="10" | 300mm | ||
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! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ | ! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ | ||
Revision as of 20:50, 26 April 2016
Semiconductor lithography processes technology
The 28 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.
Industry
| Fab |
|---|
| Wafer |
| |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HD) |
| SRAM bit cell (LP) |
| SRAM bit cell (HC) |
| Samsung | TSMC | GlobalFoundries | STMicroelectronics | UMC | |||||
|---|---|---|---|---|---|---|---|---|---|
| 300mm | |||||||||
| Value | 40 nm Δ | Value | 40 nm Δ | Value | 40 nm Δ | Value | 40 nm Δ | Value | 40 nm Δ |
| 90 nm | 0.70x | 117 nm | 0.72x | ?nm | ?x | ?nm | ?x | ?nm | ?x |
| 96 nm | 0.82x | ?nm | ?x | ?nm | ?x | ?nm | ?x | ?nm | ?x |
| 0.120 µm2 | ?x | 0.127 µm2 | 0.52x | 0.120 µm2 | ?x | 0.120 µm2 | ?x | 0.124 µm2 | ?x |
| 0.155 µm2 | 0.197 µm2 | ?x | ? µm2 | ?x | |||||
| 0.152 µm2 | ?x | ||||||||
28 nm Microprocessors
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28 nm System on Chips
- Intel
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