Semiconductor & Computer Engineering
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Difference between revisions of "90 nm lithography process"
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| 1.0 µm<sup>2</sup> || 0.50x || 0.999 µm<sup>2</sup> || 0.47x || 0.999 µm<sup>2</sup> || ?x || 1.07 µm<sup>2</sup> || 0.54x || 0.999 µm<sup>2</sup> || ?x | | 1.0 µm<sup>2</sup> || 0.50x || 0.999 µm<sup>2</sup> || 0.47x || 0.999 µm<sup>2</sup> || ?x || 1.07 µm<sup>2</sup> || 0.54x || 0.999 µm<sup>2</sup> || ?x | ||
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| + | | || || || || || || || || 0.19 µm<sup>2</sup> || ?x | ||
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Revision as of 22:23, 25 April 2016
Semiconductor lithography processes technology
The 90 nm lithography process is a full node semiconductor manufacturing process following the 110 nm process stopgap. Commercial integrated circuit manufacturing using 90 nm process began in 2003. This technology was superseded by the 80 nm process (HN) / 65 nm process (FN) in 2006.
Industry
| Fab |
|---|
| Process Name |
| 1st Production |
| Type |
| |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell |
| DRAM bit cell |
| Intel | TSMC | Samsung | Fujitsu | IBM / Toshiba / Sony / AMD / Chartered | |||||
|---|---|---|---|---|---|---|---|---|---|
| P1262 | CS-100 / CS-101 | ||||||||
| 2002 | 2003 | 2003 | 2004 | 2003 | |||||
| Bulk | PDSOI | ||||||||
| Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ | Value | 130 nm Δ |
| 260 nm | 0.82x | 240 nm | 0.77x | 245 nm | 0.70x | ? nm | ?x | ? nm | ?x |
| 220 nm | 0.63x | 240 nm | 0.71x | 245 nm | 0.70x | ? nm | ?x | ? nm | ?x |
| 1.0 µm2 | 0.50x | 0.999 µm2 | 0.47x | 0.999 µm2 | ?x | 1.07 µm2 | 0.54x | 0.999 µm2 | ?x |
| 0.19 µm2 | ?x | ||||||||
90 nm Microprocessors
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90 nm System on Chips
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90 nm Microarchitectures
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