Semiconductor & Computer Engineering
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Difference between revisions of "1.5 µm lithography process"
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| − | Intel's 1.5 µm (''P646'') was done wit 125 mm wafers. A second enhanced version in 1985 was increased to a 150 mm wafer size. | + | Intel's 1.5 µm (CHMOS III; ''P646'') was done wit 125 mm wafers. A second enhanced version in 1985 was increased to a 150 mm wafer size. |
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| − | ! [[Intel]] | + | ! [[Intel]] || [[Intel]] |
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| 1982 || 1985 | | 1982 || 1985 | ||
Revision as of 22:23, 24 April 2016
Semiconductor lithography processes technology
The 1.5 µm lithography process was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. By the late 80s this process was replaced by 1.3 µm, 1.2 µm, and 1 µm processes.
Industry
Intel's 1.5 µm (CHMOS III; P646) was done wit 125 mm wafers. A second enhanced version in 1985 was increased to a 150 mm wafer size.
| Fab |
|---|
| Process Name |
| 1st Production |
| |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell |