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  | process 1 mmp Δ        = 0.71x
 
  | process 1 mmp Δ        = 0.71x
 
  | process 1 sram hp      = 0.130 µm²
 
  | process 1 sram hp      = 0.130 µm²
−
  | process 1 sram hp Δ    =  
+
  | process 1 sram hp Δ    = 0.65x
 
  | process 1 sram hd      = 0.092 µm²
 
  | process 1 sram hd      = 0.092 µm²
−
  | process 1 sram hd Δ    =  
+
  | process 1 sram hd Δ    = 0.62x
 
  | process 1 sram lv      = 0.108 µm²
 
  | process 1 sram lv      = 0.108 µm²
−
  | process 1 sram lv Δ    =  
+
  | process 1 sram lv Δ    = 0.63x
 
  | process 1 dram        = 0.029 µm²
 
  | process 1 dram        = 0.029 µm²
 
  | process 1 dram Δ      =  
 
  | process 1 dram Δ      =  
 
<!-- Intel 22FFL -->
 
<!-- Intel 22FFL -->
 
  | process 2 fab          = [[Intel]]
 
  | process 2 fab          = [[Intel]]
−
  | process 2 name        = 22FFL
+
  | process 2 name        = 22FFL (P1222)
 
  | process 2 date        = 2017
 
  | process 2 date        = 2017
 
  | process 2 lith        = 193 nm
 
  | process 2 lith        = 193 nm
Line 49: Line 49:
 
  | process 2 wafer size  = 300 mm
 
  | process 2 wafer size  = 300 mm
 
  | process 2 transistor  = FinFET
 
  | process 2 transistor  = FinFET
−
  | process 2 volt        = &nbsp;
+
  | process 2 volt        = 0.7 V
 
  | process 2 delta from  = [[32 nm]] Δ
 
  | process 2 delta from  = [[32 nm]] Δ
 
  | process 2 fin pitch    = 45 nm
 
  | process 2 fin pitch    = 45 nm
Line 65: Line 65:
 
  | process 2 sram hp      = &nbsp;
 
  | process 2 sram hp      = &nbsp;
 
  | process 2 sram hp Δ    = -
 
  | process 2 sram hp Δ    = -
−
  | process 2 sram hd      = 0.88 µm²
+
  | process 2 sram hd      = 0.088 µm²
 
  | process 2 sram hd Δ    = -
 
  | process 2 sram hd Δ    = -
 
  | process 2 sram lv      = &nbsp;
 
  | process 2 sram lv      = &nbsp;
Line 73: Line 73:
 
<!-- Samsung -->
 
<!-- Samsung -->
 
  | process 3 fab          = [[IBM]]
 
  | process 3 fab          = [[IBM]]
−
  | process 3 name        = &nbsp;
+
  | process 3 name        = 22HP
−
  | process 3 date        = 2012
+
  | process 3 date        = 2013
 
  | process 3 lith        = 193
 
  | process 3 lith        = 193
 
  | process 3 immersion    = Yes
 
  | process 3 immersion    = Yes
Line 81: Line 81:
 
  | process 3 wafer size  = 300 mm
 
  | process 3 wafer size  = 300 mm
 
  | process 3 transistor  = Planar
 
  | process 3 transistor  = Planar
−
  | process 3 volt        = &nbsp;
+
  | process 3 volt        = 0.75 V
 
  | process 3 delta from  = [[32 nm]] Δ
 
  | process 3 delta from  = [[32 nm]] Δ
 
  | process 3 fin pitch    = -
 
  | process 3 fin pitch    = -
Line 89: Line 89:
 
  | process 3 fin height  =  
 
  | process 3 fin height  =  
 
  | process 3 fin height Δ =  
 
  | process 3 fin height Δ =  
−
  | process 3 gate len    =  
+
  | process 3 gate len    = 25-33 nm
−
  | process 3 gate len Δ  =  
+
  | process 3 gate len Δ  = 0.83-1.1x
 
  | process 3 cpp          = 100 nm
 
  | process 3 cpp          = 100 nm
−
  | process 3 cpp Δ        =  
+
  | process 3 cpp Δ        = 0.79x
 
  | process 3 mmp          = 80 nm
 
  | process 3 mmp          = 80 nm
−
  | process 3 mmp Δ        =  
+
  | process 3 mmp Δ        = 0.80x
 
  | process 3 sram hp      = 0.144 µm²
 
  | process 3 sram hp      = 0.144 µm²
−
  | process 3 sram hp Δ    =  
+
  | process 3 sram hp Δ    = &nbsp;
 
  | process 3 sram hd      = 0.128 µm²
 
  | process 3 sram hd      = 0.128 µm²
−
  | process 3 sram hd Δ    =  
+
  | process 3 sram hd Δ    = 0.86x
−
  | process 3 sram lv      =  
+
  | process 3 sram lv      = &nbsp;
−
  | process 3 sram lv Δ    =  
+
  | process 3 sram lv Δ    = &nbsp;
 
  | process 3 dram        = 0.026 µm²
 
  | process 3 dram        = 0.026 µm²
−
  | process 3 dram Δ      =  
+
  | process 3 dram Δ      = 0.67x
 
}}
 
}}
  
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| Options || High Performance (HP) || Standard Perf/Power (SP) || Low Power (LP) || Ultra-Low Power (ULP) || 1.8 V || 3.3 V
 
| Options || High Performance (HP) || Standard Perf/Power (SP) || Low Power (LP) || Ultra-Low Power (ULP) || 1.8 V || 3.3 V
 
|-
 
|-
−
| V<sub>dd</sub> (V) || 0.75 V / 1 V || 0.75 V / 1 V || 0.75 V / 1 V || 0.75 V / 1.2 V || 1.5 V / 1.8 V / 3.3 V || 3.3 V / >5V
+
| V<sub>dd</sub> (V) || 0.7 V / 1 V || 0.75 V / 1 V || 0.75 V / 1 V || 0.75 V / 1.2 V || 1.5 V / 1.8 V / 3.3 V || 3.3 V / >5V
 
|-
 
|-
 
| Gate Pitch (nm) || 90 || 90 || 90 || 108 || min. 180 || min 450
 
| Gate Pitch (nm) || 90 || 90 || 90 || 108 || min. 180 || min 450
Line 193: Line 193:
  
 
== 22 nm Microarchitectures==
 
== 22 nm Microarchitectures==
−
* Intel:
+
* Intel
−
** {{intel|Haswell}}
+
** {{intel|Haswell|l=arch}}
−
** {{intel|Ivy Bridge}}
+
** {{intel|Ivy Bridge|l=arch}}
−
** {{intel|Silvermont}}
+
** {{intel|Silvermont|l=arch}}
−
 
+
* IBM
 +
** {{ibm|POWER8|l=arch}}
 +
** {{ibm|z13|l=arch}}
 
{{expand list}}
 
{{expand list}}
  
Line 204: Line 206:
  
 
== References ==
 
== References ==
−
* Narasimha, S., et al. "22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL." Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012.
+
* IEDM 2012
−
* Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
+
* IEDM 2014
−
* Hamzaoglu, Fatih, et al. "13.1 a 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. IEEE, 2014.
+
* ISSCC 2015
−
 
 
  
−
[[Category:Lithography]]
+
[[category:lithography]]

Latest revision as of 08:52, 25 November 2020

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 22 nanometer (22 nm) lithography process is a full node semiconductor manufacturing process following the 28 nm process stopgap. The term "22 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 22 nm process began in 2008 for memory and 2012 for MPUs. This technology was replaced by with 20 nm process (HN) in 2014 and 16 nm process (FN) in late 2015.

Industry[edit]

The 22 nm became Intel's first generation of Tri-gate FinFET transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom foundry.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel Intel IBM
P1270 (CPU) / P1271 (SoC) 22FFL (P1222) 22HP
2011 2017 2013
193 nm 193 nm 193
Yes Yes Yes
SADP SADP  
Bulk Bulk SOI
300 mm 300 mm 300 mm
FinFET FinFET Planar
0.75 V 0.7 V 0.75 V
Value 32 nm Δ Value 32 nm Δ Value 32 nm Δ
60 nm N/A 45 nm N/A N/A
8 nm  
34 nm  
26 nm 30 nm 25-33 nm 0.83-1.1x
90 nm 0.80x 108 nm 100 nm 0.79x
80 nm 0.71x 90 nm 80 nm 0.80x
0.130 µm² 0.65x   0.144 µm²  
0.092 µm² 0.62x 0.088 µm² 0.128 µm² 0.86x
0.108 µm² 0.63x      
0.029 µm²     0.026 µm² 0.67x

Intel[edit]

intel 22nm tri-gate transistors.png


Find models[edit]

Click to browse all 22 nm MPU models

22 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.


Click to browse all 22 nm MPU models

22 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

Documents[edit]

References[edit]

  • IEDM 2012
  • IEDM 2014
  • ISSCC 2015
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