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Difference between revisions of "130 nm lithography process"

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{{lithography processes}}
 
{{lithography processes}}
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The '''130 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[150 nm lithography process|150 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 130 nm process began in 2001. This technology was replaced by with [[110 nm lithography process|110 nm process]] (HN) in 2003 and [[90 nm lithography process|90 nm process]] (FN) in 2004.
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The '''130 nanometer (130 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[150 nm lithography process|150 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 130 nm process began in 2001. This technology was replaced by with [[110 nm lithography process|110 nm process]] (HN) in 2003 and [[90 nm lithography process|90 nm process]] (FN) in 2004.
  
 
== Industry ==
 
== Industry ==
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  |1st Production
 
  |1st Production
 
  |Type
 
  |Type
 +
|Wafer
 +
|Metal Layers
 
  | 
 
  | 
 
  |Contacted Gate Pitch
 
  |Contacted Gate Pitch
 
  |Interconnect Pitch (M1P)
 
  |Interconnect Pitch (M1P)
−
  |SRAM bit cell
+
  |SRAM bit cell (HP)​
 +
|SRAM bit cell (HD)​
 
}}
 
}}
 
{{scrolling table/mid}}
 
{{scrolling table/mid}}
 
|-
 
|-
−
! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[IBM]]
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! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[IBM]] / [[Infineon]] / [[UMC]] !! colspan="2" | [[Motorola]] !! colspan="2" | [[AMD]] !! colspan="2" | [[NEC]] !! colspan="2" | [[NEC]] !! colspan="2" | [[TI]] !! colspan="2" | [[TI]]
 
|- style="text-align: center;"
 
|- style="text-align: center;"
−
| colspan="2" | P860 || colspan="2" |  || colspan="2" | || colspan="2" | CS-91 || colspan="2" |  
+
| colspan="2" | P860 || colspan="2" |  || colspan="2" | || colspan="2" | CS-91 || colspan="2" | CMOS 9S || colspan="2" | HiPerMOS 7 || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  
 
|- style="text-align: center;"
 
|- style="text-align: center;"
−
| colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001
+
| colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2002 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" | 2001 || colspan="2" |
 
|- style="text-align: center;"
 
|- style="text-align: center;"
−
| colspan="8" | Bulk || colspan="2" | PDSOI
+
| colspan="8" | Bulk || colspan="2" | PDSOI || colspan="12" | Bulk
 +
|- style="text-align: center;"
 +
| colspan="22" | 200 mm
 +
|- style="text-align: center;"
 +
| colspan="2" | 6 || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" | 8 || colspan="2" | 8 || colspan="2" |  || colspan="2" | 5 || colspan="2" | 7 || colspan="2" | 6 || colspan="2" | 7
 +
|-
 +
! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ
 
|-
 
|-
−
! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ !! Value !! [[180 nm]] Δ
+
| 319 nm || 0.66x || 310 nm || 0.72x || 350 nm || ?x || ? nm || ?x || 320 nm || 0.76x || 350 nm || ?x || 350 nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x
 
|-
 
|-
−
| 319 nm || 0.66x || 310 nm || ?x || 350 nm || ?x || ? nm || ?x || 350 nm || ?x
+
| 345 nm || 0.69x || 340 nm || 0.74x || 350 nm || ?x || ? nm || ?x || 320 nm || 0.73x || 350 nm || ?x || 350 nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x
 
|-
 
|-
−
| 345 nm || 0.69x || 340 nm || ?x || 350 nm || ?x || ? nm || ?x || ? nm || ?x
+
| 2.45 µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x  || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x  
 
|-
 
|-
−
| 2.0 µm<sup>2</sup> || 0.36x || 2.14 µm<sup>2</sup> || 0.46x || ? µm<sup>2</sup> || ?x || 1.98 µm<sup>2</sup> || 0.47x || 1.8 µm<sup>2</sup> || ?x
+
| 2.09 µm² || 0.36x || 2.14 µm² || 0.46x || ? µm² || ?x || 1.98 µm² || 0.47x || 1.8 µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x  
 
{{scrolling table/end}}
 
{{scrolling table/end}}
 
=== Design Rules ===
 
=== Design Rules ===
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== 130 nm Microprocessors==
 
== 130 nm Microprocessors==
 +
* Ambric
 +
** {{ambric|Am2000}}
 +
* AMD
 +
** {{amd|Athlon 64}}
 +
** {{amd|Athlon MP}}
 +
** {{amd|Athlon XP}}
 +
** {{amd|Athlon XP-M}}
 +
** {{amd|Geode NX}}
 +
** {{amd|FX}}
 +
** {{amd|Opteron}}
 +
* Cavium
 +
** {{cavium|OCTEON}}
 +
* HAL (Fujitsu)
 +
** {{hal|SPARC64 V}}
 +
* IBM
 +
** {{ibm|Power4+}}
 +
** {{ibm|Power5}}
 
* Intel
 
* Intel
 
** {{intel|Pentium III}}
 
** {{intel|Pentium III}}
 
** {{intel|Pentium III-M}}
 
** {{intel|Pentium III-M}}
 +
** {{intel|Pentium M}}
 
** {{intel|Pentium 4 Extreme Edition}}
 
** {{intel|Pentium 4 Extreme Edition}}
 +
* Intrinsity
 +
** {{intrinsity|FastMATH}}
 +
* Loongson
 +
** {{loongson|Godson 2}}
 +
* Qualcomm
 +
** {{qualcomm|MSM6xxx}}
 +
* SGI
 +
** {{sgi|R14000}}
 +
** {{sgi|R14000A}}
 +
* Sun
 +
** {{sun|UltraSPARC IIi}}
 +
** {{sun|UltraSPARC III Cu}}
 +
** {{sun|UltraSPARC IIIi}}
 +
 +
* NUDT
 +
** {{nudt|FT-64}}
 +
{{expand list}}
 +
 +
== 130 nm programmable logic devices ==
 +
* MathStar
 +
** {{mathstar|Builder}}
 
{{expand list}}
 
{{expand list}}
  
 
== 130 nm Microarchitectures ==
 
== 130 nm Microarchitectures ==
 +
* AMD
 +
** {{amd|K8|l=arch}}
 +
* ARM
 +
** {{armh|ARM7|l=arch}}
 +
* IBM
 +
** {{ibm|z990|l=arch}}
 +
* VIA Technologies
 +
** {{via|Nehemiah|l=arch}}
 
{{expand list}}
 
{{expand list}}
 +
 +
== References ==
 +
* Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects." Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. IEEE, 2000.
 +
 +
[[category:lithography]]

Latest revision as of 15:02, 13 May 2020

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 130 nanometer (130 nm) lithography process is a full node semiconductor manufacturing process following the 150 nm process stopgap. Commercial integrated circuit manufacturing using 130 nm process began in 2001. This technology was replaced by with 110 nm process (HN) in 2003 and 90 nm process (FN) in 2004.

Industry[edit]

Fab
Process Name​
1st Production​
Type​
Wafer​
Metal Layers​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HP)​​
SRAM bit cell (HD)​
Intel TSMC Samsung Fujitsu IBM / Infineon / UMC Motorola AMD NEC NEC TI TI
P860 CS-91 CMOS 9S HiPerMOS 7
2001 2001 2001 2002 2001 2001 2002 2001 2001 2001
Bulk PDSOI Bulk
200 mm
6 8 8 5 7 6 7
Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ
319 nm 0.66x 310 nm 0.72x 350 nm  ?x  ? nm  ?x 320 nm 0.76x 350 nm  ?x 350 nm  ?x  ?nm  ?x  ?nm  ?x  ?nm  ?x  ?nm  ?x
345 nm 0.69x 340 nm 0.74x 350 nm  ?x  ? nm  ?x 320 nm 0.73x 350 nm  ?x 350 nm  ?x  ?nm  ?x  ?nm  ?x  ?nm  ?x  ?nm  ?x
2.45 µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x
2.09 µm² 0.36x 2.14 µm² 0.46x  ? µm²  ?x 1.98 µm² 0.47x 1.8 µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x

Design Rules[edit]

130 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

130 nm programmable logic devices[edit]

This list is incomplete; you can help by expanding it.

130 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

References[edit]

  • Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects." Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. IEEE, 2000.
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