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Difference between revisions of "1.5 µm lithography process"

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{{Lithography processes}}
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{{lithography processes}}
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The '''1.5μm lithography process''' was the semiconductor process technology used by some semiconductor companies between 1982 to 1985.
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The '''1.5 µm lithography process''' was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. This process had an effective channel length of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by [[1.3 µm]], [[1.2 µm]], and [[1 µm]] processes.
  
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== Microprocessors ==
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== Industry ==
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* [[Intel 80286]]
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{{scrolling table/top|style=text-align: right; | first=Fab
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* [[Intel 80386]]
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|Process Name
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|1st Production
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|Contacted Gate Pitch
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|Interconnect Pitch (M1P)
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|Metal Layers​
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|SRAM bit cell
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|Wafer
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}}
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{{scrolling table/mid}}
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|-
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! [[Intel]] || [[Intel]] || [[Intel]] || [[HP]] || [[AMD]] || [[DEC]]
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|- style="text-align: center;"
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| HMOS-II || HMOS-E || P646 (CHMOS III) || NMOS III || || CMOS-2
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|- style="text-align: center;"
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| 1982 || 1982 || 1985 || 1981 || 1982 ||
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|-
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| ? nm || ? nm  || ? nm  || 1.5 µm || ||
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|-
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| ? nm ||  ? nm || ? nm || 2.5 µm || ||
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|-
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| 2 || ? || 2 || 2 || 2 || 2
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|-
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| ? µm² ||  ? µm² ||  ? µm² || ? µm² || ? µm² ||
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|-
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| 125 mm  || || 150 mm  ||  || ||
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{{scrolling table/end}}
  
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{{stub}}
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=== HP ===
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[[Category:Lithography]]
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{| class="wikitable collapsible collapsed"
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|-
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! colspan="3" | [[HP]] NMOS-III Design Rules
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|-
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! Layer !! Description
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|-
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| Oxide || 450 nm thick silicon dioxide<br>1.5 µm x 1.5 µm minimum contact area, zero overlap to polysilicon, zero overlap of first metal layer
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|-
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| M1 || 1.5 µm wide line / 1.0 µm space<br>0.4 ohm/square sheet resistance
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|-
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| Intemediate Oxide || 550 nm-thick silicon dioxide<br>1.5 µm x 2.0 µm minimum contact area, zero overlap to first metal layer<br>2.0 µm overlap of second metal layer to via
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|-
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| M2 || 5.0 µm wide line / 3.0 µm space<br>0.4 ohm/square sheet resistance
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|}
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=== DEC ===
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[[DEC]] operated their 1.5 µm process ('''CMOS-2''') at their Hudson foundry. This 2 ML process had an effective channel length of 0.9 µm with a polycide width of 1.5 µm (1.5 µm spacing) and a T<sub>OX</sub> of 22.5 nm.
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{| class="wikitable collapsible collapsed"
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|-
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! colspan="2" | [[DEC]] Design Rules
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|-
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! !! Width !! Spacing
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|-
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| Polycide || 1.5 µm || 1.5 µm
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|-
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| Metal 1 || 3 µm || 1.5 µm
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|-
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| Metal 1 Contact || 1.5 µm x 1.5 µm
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|-
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| Metal 2 || 3.75 µm || 1.5
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|-
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| Metal 2 Contact || 1.5 µm x 1.5 µm
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|}
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== 1.5 µm Microprocessors ==
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* AMD
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** {{amd|Am186}}
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** {{amd|Am286}}
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* Intel
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** {{intel|80286}}
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** {{intel|80386 DX}}
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** {{intel|80387}}
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* HP
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** {{hp|FOCUS}}
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* Dec
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** {{decc|Rigel}}
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{{expand list}}
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== 1.5 µm Microarchitectures ==
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* ARM
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** {{armh|ARM3|l=arch}}
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* Intel
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** {{intel|80386|l=arch}}
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{{expand list}}
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* DEC
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** {{decc|MicroPrism|l=arch}}
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** {{decc|MicroTitan|l=arch}}
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[[category:lithography]]

Latest revision as of 22:04, 20 May 2018

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 1.5 µm lithography process was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. This process had an effective channel length of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by 1.3 µm, 1.2 µm, and 1 µm processes.

Industry[edit]

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
Metal Layers​​
SRAM bit cell​
Wafer
Intel Intel Intel HP AMD DEC
HMOS-II HMOS-E P646 (CHMOS III) NMOS III CMOS-2
1982 1982 1985 1981 1982
 ? nm  ? nm  ? nm 1.5 µm
 ? nm  ? nm  ? nm 2.5 µm
2  ? 2 2 2 2
 ? µm²  ? µm²  ? µm²  ? µm²  ? µm²
125 mm 150 mm

HP[edit]

DEC[edit]

DEC operated their 1.5 µm process (CMOS-2) at their Hudson foundry. This 2 ML process had an effective channel length of 0.9 µm with a polycide width of 1.5 µm (1.5 µm spacing) and a TOX of 22.5 nm.

1.5 µm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

1.5 µm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

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