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{{lithography processes}}
 
{{lithography processes}}
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The '''65 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[80 nm lithography process|80 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 65 nm process began in 2006. This technology was superseded by the [[55 nm lithography process|55 nm process]] (HN) / [[45 nm lithography process|45 nm process]] (FN) in 2007.
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The '''65 nanometer (65 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[80 nm lithography process|80 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 65 nm process began in 2005. This technology was superseded by the [[55 nm lithography process|55 nm process]] (HN) / [[45 nm lithography process|45 nm process]] (FN) in 2007.
  
 
== Industry ==
 
== Industry ==
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{{scrolling table/top|style=text-align: right; | first=Fab
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=== Intel ===
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|Process Name
−
{| class="wikitable"
+
|1st Production
 +
|Wafer
 +
|Metal Layers
 +
| 
 +
|Contacted Gate Pitch
 +
|Interconnect Pitch (M1P)
 +
|SRAM bit cell (HD)
 +
|SRAM bit cell (LP)
 +
|DRAM bit cell
 +
}}
 +
{{scrolling table/mid}}
 +
|-
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! colspan="2" | [[Intel]] !! colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] !! colspan="2" | [[TI]] !! colspan="2" | [[IBM]] / [[Chartered]] / [[Infineon]] / [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Fujitsu]]
 +
|- style="text-align: center;"
 +
| colspan="2" | P1264 || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" |  || colspan="2" | CS-200/CS-201/CS-250
 +
|- style="text-align: center;"
 +
| colspan="2" | 2005 || colspan="2" | 2005 || colspan="2" | 2007 || colspan="2" | 2005 || colspan="2" | 2005 || colspan="2" | 2006
 +
|- style="text-align: center;"
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| colspan="12" | 300mm
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|- style="text-align: center;"
 +
| colspan="2" | 8 || colspan="2" | 10 || colspan="2" | 11 || colspan="2" | 10 || colspan="2" | || colspan="2" | 11
 +
|-
 +
! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ
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|-
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| 220 nm || 0.85x || 250 nm || ?x || ? nm || ?x || 200 nm || 0.82x || 160 nm  || 0.67x || ? nm || ?x
 
|-
 
|-
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| || Measurement || Scaling from [[90 nm]]
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| 210 nm || 0.95x || ? nm || ?x || ? nm || ?x || 180 nm || 0.73 || 180 nm || 0.75x || ? nm || ?x
 
|-
 
|-
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| Contacted Gate Pitch || 220 nm || 0.85x
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| 0.570 µm² || 0.57x || 0.540 µm² ||  || 0.49 µm² || || 0.540 µm² || 0.55x || 0.499 µm² || 0.50x || ||
 
|-
 
|-
−
| Interconnect Pitch (M1P) || 210 nm || 0.95x
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| 0.680 µm² || || 0.65 µm² || 0.65x || 0.49 µm² || || 0.676 µm² || 0.54x || 0.525 µm² || 0.53x || ? µm² || ?x
 
|-
 
|-
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| [[SRAM]] bit cell || 0.570 µm<sup>2</sup> || 0.61x
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| || || 0.127 µm² || 0.67x || || || 0.189 µm² || 0.69x || || || ||
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|}
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{{scrolling table/end}}
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=== Design Rules ===
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{| class="wikitable"
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{| class="wikitable collapsible collapsed"
 
|-
 
|-
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! colspan="4" | Design Rules
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! colspan="4" | Intel 65nm Design Rules
 
|-
 
|-
 
! Layer !! Pitch !! Thick !! Aspect Ratio
 
! Layer !! Pitch !! Thick !! Aspect Ratio
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== 65 nm Microprocessors==
 
== 65 nm Microprocessors==
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{{expand list}}
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* AMD
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** {{amd|Athlon 64 X2}}
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== 65 nm System on Chips==
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** {{amd|Athlon X2}}
 +
** {{amd|Opteron}}
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** {{amd|Phenom}}
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** {{amd|Turion 64 X2}}
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* Fujitsu
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** {{fujitsu|SPARC64 VII}}
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* IBM
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** {{ibm|Power6}}
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* Intel
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** {{intel|Celeron}}
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** {{intel|Core 2 Duo}}
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** {{intel|Core 2 Extreme}}
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** {{intel|Core 2 Quad}}
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** {{intel|Core 2 Quad Extreme}}
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** {{intel|Core Duo}}
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** {{intel|Pentium 4}}
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** {{intel|Pentium D}}
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** {{intel|Pentium Extreme Edition}}
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** {{intel|Pentium Dual-Core}}
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** {{intel|Xeon}}
 +
* Loongson
 +
** {{loongson|Godson 2}}
 +
* Qualcomm
 +
** {{qualcomm|MSM6xxx}}
 +
* Sun
 +
** {{sun|UltraSPARC T2}}
 
{{expand list}}
 
{{expand list}}
  
 
== 65 nm Microarchitectures ==
 
== 65 nm Microarchitectures ==
 +
* AMD
 +
** {{amd|K8|l=arch}}
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** {{amd|K10|l=arch}}
 +
* ARM
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** {{armh|ARM7|l=arch}}
 +
* IBM
 +
** {{ibm|z10|l=arch}}
 
* Intel
 
* Intel
−
** {{intel|Core (arch)|Core}}
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** {{intel|Core|l=arch}}
 +
* Movidius
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** {{movidius|SHAVE v2.0|l=arch}}
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* VIA Technologies
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** {{via|Isaiah|l=arch}}
 
{{expand list}}
 
{{expand list}}
 +
 +
== Documents ==
 +
* [[:File:samsung foundry - 45, 65, 90 (August, 2007).pdf|Samsung foundry - 45 nm, 65 nm, 90 nm guide (August, 2007)]]
 +
 +
[[category:lithography]]

Latest revision as of 04:55, 20 July 2018

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 65 nanometer (65 nm) lithography process is a full node semiconductor manufacturing process following the 80 nm process stopgap. Commercial integrated circuit manufacturing using 65 nm process began in 2005. This technology was superseded by the 55 nm process (HN) / 45 nm process (FN) in 2007.

Industry[edit]

Fab
Process Name​
1st Production​
Wafer​
Metal Layers​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HD)​
SRAM bit cell (LP)​
DRAM bit cell
Intel IBM / Toshiba / Sony / AMD TI IBM / Chartered / Infineon / Samsung TSMC Fujitsu
P1264 CS-200/CS-201/CS-250
2005 2005 2007 2005 2005 2006
300mm
8 10 11 10 11
Value 90 nm Δ Value 90 nm Δ Value 90 nm Δ Value 90 nm Δ Value 90 nm Δ Value 90 nm Δ
220 nm 0.85x 250 nm  ?x  ? nm  ?x 200 nm 0.82x 160 nm 0.67x  ? nm  ?x
210 nm 0.95x  ? nm  ?x  ? nm  ?x 180 nm 0.73 180 nm 0.75x  ? nm  ?x
0.570 µm² 0.57x 0.540 µm² 0.49 µm² 0.540 µm² 0.55x 0.499 µm² 0.50x
0.680 µm² 0.65 µm² 0.65x 0.49 µm² 0.676 µm² 0.54x 0.525 µm² 0.53x  ? µm²  ?x
0.127 µm² 0.67x 0.189 µm² 0.69x

Design Rules[edit]

65 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

65 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

Documents[edit]

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