Semiconductor & Computer Engineering
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Difference between revisions of "10 µm lithography process"
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| − | The '''10 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1967 and 1973. The typical [[wafer]] | + | The '''10 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this process at companies such as [[Fairchild]] and [[TI]] was 2-inch (51 mm). |
== Industry == | == Industry == | ||
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{{scrolling table/mid}} | {{scrolling table/mid}} | ||
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| − | ! [[Intel]] !! [[TI]] !! [[RCA]] !! [[Fairchild]] !! [[National Semiconductor|National]] | + | ! [[Intel]] !! [[TI]] !! [[RCA]] !! [[Fairchild]] !! [[National Semiconductor|National]]!! [[microsystems international|MIL]] |
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|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | 1970 || 1969 || 1969 || || | + | | 1970 || 1969 || 1969 || || || 1969 |
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| − | | ? nm || ? nm || ? nm || ? nm || ? nm | + | | ? nm || ? nm || ? nm || ? nm || ? nm || ? nm |
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| − | | ? nm || ? nm || ? nm || ? nm || ? nm | + | | ? nm || ? nm || ? nm || ? nm || ? nm || ? nm |
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| − | | 2 || 2 || 2 || 2 || | + | | 2 || 2 || 2 || 2 || || |
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| − | | PMOS || PMOS || CMOS || PMOS || PMOS | + | | PMOS || PMOS || CMOS || PMOS || PMOS || |
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| − | | 51 mm || || || || | + | | 51 mm || || || || || |
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** {{intel|MCS-40|4040}} | ** {{intel|MCS-40|4040}} | ||
** {{intel|MCS-8|8008}} | ** {{intel|MCS-8|8008}} | ||
| + | * National | ||
| + | ** {{national|IMP-4}} | ||
{{expand list}} | {{expand list}} | ||
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| searchlabel=Click to browse all 10 µm models | | searchlabel=Click to browse all 10 µm models | ||
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== 10 µm Chips == | == 10 µm Chips == | ||
* Intel | * Intel | ||
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{{stub}} | {{stub}} | ||
| − | [[ | + | [[category:lithography]] |
Latest revision as of 22:04, 20 May 2018
Semiconductor lithography processes technology
The 10 µm lithography process was the semiconductor process technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process at companies such as Fairchild and TI was 2-inch (51 mm).
Industry[edit]
| Fab |
|---|
| Process Name |
| 1st Production |
| Contacted Gate Pitch |
| Interconnect Pitch |
| Metal Layers |
| Technology |
| Wafer |
| Intel | TI | RCA | Fairchild | National | MIL |
|---|---|---|---|---|---|
| 1970 | 1969 | 1969 | 1969 | ||
| ? nm | ? nm | ? nm | ? nm | ? nm | ? nm |
| ? nm | ? nm | ? nm | ? nm | ? nm | ? nm |
| 2 | 2 | 2 | 2 | ||
| PMOS | PMOS | CMOS | PMOS | PMOS | |
| 51 mm |
10 µm Microprocessors[edit]
This list is incomplete; you can help by expanding it.
Click to browse all 10 µm models
10 µm Chips[edit]
- Intel
- RCA
This list is incomplete; you can help by expanding it.
 |
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |