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The '''10μm lithography process''' was the semiconductor process technology used by the major semiconductor companies during the years of 1970 and 1973. The first microprocessors, such as the [[Intel]] [[Intel 4004|4004]] and the [[Intel 4040|4040]] used 10μm technology.
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The '''10 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this process at companies such as [[Fairchild]] and [[TI]] was 2-inch (51 mm).
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== Industry ==
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{{scrolling table/top|style=text-align: right; | first=Fab
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|Process Name
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|1st Production
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|Contacted Gate Pitch
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|Interconnect Pitch
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|Metal Layers
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|Technology
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|Wafer
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}}
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{{scrolling table/mid}}
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|-
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! [[Intel]] !! [[TI]] !! [[RCA]] !! [[Fairchild]] !! [[National Semiconductor|National]]!! [[microsystems international|MIL]]
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|- style="text-align: center;"
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|  || || || || ||  
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|- style="text-align: center;"
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| 1970 || 1969 || 1969 || || || 1969
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|-
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| ? nm  || ? nm || ? nm  || ? nm || ? nm || ? nm
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|-
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| ? nm  || ? nm || ? nm  || ? nm || ? nm || ? nm
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|-
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| 2 || 2 || 2 || 2 || ||
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|-
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| PMOS || PMOS || CMOS || PMOS || PMOS ||
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|-
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| 51 mm || || || || ||
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{{scrolling table/end}}
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== 10 µm Microprocessors ==
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* Intel
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** {{intel|MCS-4|4004}}
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** {{intel|MCS-40|4040}}
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** {{intel|MCS-8|8008}}
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* National
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** {{national|IMP-4}}
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{{expand list}}
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{{#ask:
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[[instance of::microprocessor]]
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[[process::10 µm]]
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| ?name
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| ?process
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| ?manufacturer
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| format=broadtable
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| limit=0
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| sep=,
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| searchlabel=Click to browse all 10 µm models
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}}
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== 10 µm Chips ==
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* Intel
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** {{intel|3000}}
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* RCA
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** {{rca|CD4000|CD4000 Series}}
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{{expand list}}
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{{stub}}
 
{{stub}}
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[[Category:Lithography]]
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[[category:lithography]]

Latest revision as of 22:04, 20 May 2018

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 10 µm lithography process was the semiconductor process technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process at companies such as Fairchild and TI was 2-inch (51 mm).

Industry[edit]

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch​
Metal Layers​
Technology​
Wafer
Intel TI RCA Fairchild National MIL
 
1970 1969 1969 1969
 ? nm  ? nm  ? nm  ? nm  ? nm  ? nm
 ? nm  ? nm  ? nm  ? nm  ? nm  ? nm
2 2 2 2
PMOS PMOS CMOS PMOS PMOS
51 mm

10 µm Microprocessors[edit]

This list is incomplete; you can help by expanding it.


Click to browse all 10 µm models

10 µm Chips[edit]

This list is incomplete; you can help by expanding it.


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