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<!-- Samsung --> | <!-- Samsung --> | ||
| process 4 fab = [[Samsung]] | | process 4 fab = [[Samsung]] | ||
− | | process 4 name = | + | | process 4 name = 3LLP<info>3nm Low Power Plus</info> |
| process 4 date = | | process 4 date = | ||
| process 4 lith = EUV | | process 4 lith = EUV | ||
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| process 4 dram Δ = | | process 4 dram Δ = | ||
}} | }} | ||
+ | |||
+ | === Samsung === | ||
+ | On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown. | ||
== 3.5 nm Microprocessors== | == 3.5 nm Microprocessors== |
Revision as of 13:54, 1 June 2017
The 3.5 nanometer (3.5 nm) or 35 Å lithography process is a full node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3.5 nm process is set to begin sometimes around 2024 or 2025. The term "3.5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.
Industry
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Intel | TSMC | GlobalFoundries | Samsung | ||||
---|---|---|---|---|---|---|---|
P1280? (CPU), P1281? (SoC) | 3LLP 3nm Low Power Plus
| ||||||
EUV | EUV | EUV | EUV | ||||
SE | SE | SE | SE | ||||
Bulk | Bulk | Bulk | Bulk | ||||
300 nm | 300 nm | 300 nm | 300 nm | ||||
GAA | |||||||
Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ |
N/A | |||||||
Samsung
On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.
3.5 nm Microprocessors
This list is incomplete; you can help by expanding it.
3.5 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017