Difference between revisions of "3 nm lithography process"

Revision as of 13:53, 1 June 2017

Semiconductor lithography processes technology

1 nm • 18A
2 nm • 3 nm
5 nm • 7 nm
10 nm • 12 nm
14 nm • 16 nm
20 nm • 22 nm
28 nm • 32 nm
40 nm • 45 nm
55 nm • 65 nm
80 nm • 90 nm
110 nm • 130 nm
150 nm • 180 nm
220 nm • 240 nm
250 nm • 280 nm
350 nm • 500 nm
600 nm • 650 nm
700 nm • 750 nm
800 nm
1 µm • 1.2 µm
1.3 µm • 1.5 µm
2 µm • 2.5 µm
3 µm • 3.5 µm
5 µm • 6 µm
7 µm • 8 µm
10 µm • 16 µm
20 µm • 50 µm

The 3.5 nanometer (3.5 nm) or 35 Å lithography process is a full node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3.5 nm process is set to begin sometimes around 2024 or 2025. The term "3.5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.

Industry

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


Process Name
1st Production
Litho- graphy	Lithography
	Immersion
	Exposure
Wafer	Type
Wafer	Size
Tran- sistor	Type
Tran- sistor	Voltage

Fin	Pitch
	Width
	Height
Gate Length (L_g)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell	High-Perf (HP)
	High-Density (HD)
	Low-Voltage (LV)
DRAM bitcell	eDRAM

 Intel
 TSMC
 GlobalFoundries
 Samsung

 P1280? (CPU), P1281? (SoC)
  
 EUV
 EUV
 EUV
 EUV

 SE
 SE
 SE
 SE

 Bulk
 Bulk
 Bulk
 Bulk

 300 nm
 300 nm
 300 nm
 300 nm

 GAA

 Value 
 5 nm Δ
 Value 
 5 nm Δ
 Value 
 5 nm Δ
 Value 
 5 nm Δ

 N/A

3.5 nm Microprocessors

This list is incomplete; you can help by expanding it.

3.5 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References

Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017

@@ Line 1: / Line 1: @@
 {{lithography processes}}
 The '''3.5 nanometer (3.5 nm)''' or '''35 Å lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3.5 nm process is set to begin sometimes around 2024 or 2025. The term "3.5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to [[technology node|gate length or half pitch]].
 == Industry ==
-{{empty section}}
+{{future information}}
+{{finfet nodes comp
+<!-- Intel -->
+ | process 1 fab          = [[Intel]]
+ | process 1 name         = P1280? (CPU), P1281? (SoC)
+ | process 1 date         = &nbsp;
+ | process 1 lith         = EUV
+ | process 1 immersion    = &nbsp;
+ | process 1 exposure     = SE
+ | process 1 wafer type   = Bulk
+ | process 1 wafer size   = 300 nm
+ | process 1 transistor   = &nbsp;
+ | process 1 volt         = &nbsp;
+ | process 1 delta from   = [[5 nm]] Δ
+ | process 1 fin pitch    = &nbsp;
+ | process 1 fin pitch Δ  = &nbsp;
+ | process 1 fin width    = &nbsp;
+ | process 1 fin width Δ  = &nbsp;
+ | process 1 fin height   = &nbsp;
+ | process 1 fin height Δ = &nbsp;
+ | process 1 gate len     = &nbsp;
+ | process 1 gate len Δ   = &nbsp;
+ | process 1 cpp          = &nbsp;
+ | process 1 cpp Δ        = &nbsp;
+ | process 1 mmp          = &nbsp;
+ | process 1 mmp Δ        = &nbsp;
+ | process 1 sram hp      = &nbsp;
+ | process 1 sram hp Δ    = &nbsp;
+ | process 1 sram hd      = &nbsp;
+ | process 1 sram hd Δ    = &nbsp;
+ | process 1 sram lv      = &nbsp;
+ | process 1 sram lv Δ    = &nbsp;
+ | process 1 dram         = &nbsp;
+ | process 1 dram Δ       = &nbsp;
+<!-- TSMC -->
+ | process 2 fab          = [[TSMC]]
+ | process 2 name         = &nbsp;
+ | process 2 date         = &nbsp;
+ | process 2 lith         = EUV
+ | process 2 immersion    = &nbsp;
+ | process 2 exposure     = SE
+ | process 2 wafer type   = Bulk
+ | process 2 wafer size   = 300 nm
+ | process 2 transistor   = &nbsp;
+ | process 2 volt         = &nbsp;
+ | process 2 delta from   = [[5 nm]] Δ
+ | process 2 fin pitch    = &nbsp;
+ | process 2 fin pitch Δ  = &nbsp;
+ | process 2 fin width    = &nbsp;
+ | process 2 fin width Δ  = &nbsp;
+ | process 2 fin height   = &nbsp;
+ | process 2 fin height Δ = &nbsp;
+ | process 2 gate len     = &nbsp;
+ | process 2 gate len Δ   = &nbsp;
+ | process 2 cpp          = &nbsp;
+ | process 2 cpp Δ        = &nbsp;
+ | process 2 mmp          = &nbsp;
+ | process 2 mmp Δ        = &nbsp;
+ | process 2 sram hp      = &nbsp;
+ | process 2 sram hp Δ    = &nbsp;
+ | process 2 sram hd      = &nbsp;
+ | process 2 sram hd Δ    = &nbsp;
+ | process 2 sram lv      = &nbsp;
+ | process 2 sram lv Δ    = &nbsp;
+ | process 2 dram         = &nbsp;
+ | process 2 dram Δ       = &nbsp;
+<!-- GlobalFoundries -->
+ | process 3 fab          = [[GlobalFoundries]]
+ | process 3 name         = &nbsp;
+ | process 3 date         = &nbsp;
+ | process 3 lith         = EUV
+ | process 3 immersion    = &nbsp;
+ | process 3 exposure     = SE
+ | process 3 wafer type   = Bulk
+ | process 3 wafer size   = 300 nm
+ | process 3 transistor   = &nbsp;
+ | process 3 volt         = &nbsp;
+ | process 3 delta from   = [[5 nm]] Δ
+ | process 3 fin pitch    = &nbsp;
+ | process 3 fin pitch Δ  = &nbsp;
+ | process 3 fin width    = &nbsp;
+ | process 3 fin width Δ  = &nbsp;
+ | process 3 fin height   = &nbsp;
+ | process 3 fin height Δ = &nbsp;
+ | process 3 gate len     = &nbsp;
+ | process 3 gate len Δ   = &nbsp;
+ | process 3 cpp          = &nbsp;
+ | process 3 cpp Δ        = &nbsp;
+ | process 3 mmp          = &nbsp;
+ | process 3 mmp Δ        = &nbsp;
+ | process 3 sram hp      = &nbsp;
+ | process 3 sram hp Δ    = &nbsp;
+ | process 3 sram hd      = &nbsp;
+ | process 3 sram hd Δ    = &nbsp;
+ | process 3 sram lv      = &nbsp;
+ | process 3 sram lv Δ    = &nbsp;
+ | process 3 dram         = &nbsp;
+ | process 3 dram Δ       = &nbsp;
+<!-- Samsung -->
+ | process 4 fab          = [[Samsung]]
+ | process 4 name         = &nbsp;
+ | process 4 date         = &nbsp;
+ | process 4 lith         = EUV
+ | process 4 immersion    = &nbsp;
+ | process 4 exposure     = SE
+ | process 4 wafer type   = Bulk
+ | process 4 wafer size   = 300 nm
+ | process 4 transistor   = GAA
+ | process 4 volt         = &nbsp;
+ | process 4 delta from   = [[5 nm]] Δ
+ | process 4 fin pitch    = -
+ | process 4 fin pitch Δ  =
+ | process 4 fin width    =
+ | process 4 fin width Δ  =
+ | process 4 fin height   =
+ | process 4 fin height Δ =
+ | process 4 gate len     = &nbsp;
+ | process 4 gate len Δ   = &nbsp;
+ | process 4 cpp          = &nbsp;
+ | process 4 cpp Δ        = &nbsp;
+ | process 4 mmp          = &nbsp;
+ | process 4 mmp Δ        = &nbsp;
+ | process 4 sram hp      = &nbsp;
+ | process 4 sram hp Δ    = &nbsp;
+ | process 4 sram hd      = &nbsp;
+ | process 4 sram hd Δ    = &nbsp;
+ | process 4 sram lv      = &nbsp;
+ | process 4 sram lv Δ    = &nbsp;
+ | process 4 dram         = &nbsp;
+ | process 4 dram Δ       = &nbsp;
+}}
 == 3.5 nm Microprocessors==
@@ Line 10: / Line 143: @@
 == 3.5 nm Microarchitectures==
 {{expand list}}
+== References ==
+* Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after [[5 nm]], May 24, 2017
 [[Category:Lithography]]

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas