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Difference between revisions of "5 µm lithography process"

(Created page with "{{Lithography processes}} The '''5μm lithography process''' was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process w...")
 
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== Industry ==
 
== Industry ==
HP's ''NMOS II'' process as the name implied was a second generation nMOD process which was a shrink of their previous generation [[7 µm]] nMOS also developed by [[HP]]'s Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the ''NMOS III'' using a [[1.5 µm process]]
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HP's ''NMOS II'' process as the name implied was a second generation nMOD process which was a shrink of their previous generation [[7 µm]] nMOS also developed by [[HP]]'s Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the ''NMOS III'' using a [[1.5 µm process]].
 
{{scrolling table/top|style=text-align: right; | first=Fab
 
{{scrolling table/top|style=text-align: right; | first=Fab
 
  |Process Name
 
  |Process Name

Revision as of 09:26, 26 April 2016

The 5μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process was later superseded by 3 µm, 2 µm, and 1.5 µm processes.

Industry

HP's NMOS II process as the name implied was a second generation nMOD process which was a shrink of their previous generation 7 µm nMOS also developed by HP's Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the NMOS III using a 1.5 µm process.

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch​
Metal Layers​
Technology​
Wafer
HP
NMOS II
1973
 ? nm
 ? nm
 
nMOS
51 mm

5µm Microprocessors


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