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7 nm lithography process
Revision as of 06:51, 15 November 2016 by 146.103.254.11 (talk) (added TSMC SRAM size)

The 7 nanometer (7 nm) lithography process is a full node semiconductor manufacturing process following the 10 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes in 2019 or 2020. This technology will be replaced by 5 nm process around 2022.

Industry

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


Fab
Process Name​
1st Production​
 ​
Fin Pitch​
Fin Width​
Fin Height​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HP)​
SRAM bit cell (HD)
Intel Samsung TSMC
P1276
 
Value 10 nm Δ Value 10 nm Δ Value 10 nm Δ
 ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x 48 nm[1]  ?x  ? nm  ?x
 ? nm  ?x 36 nm[2]  ?x  ? nm  ?x
 ? µm2  ?x  ? µm2  ?x  ? µm2  ?x
 ? µm2  ?x  ? µm2  ?x 0.027 µm2[3]  ?x

7 nm Microprocessors

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7 nm System on Chips

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7 nm Microarchitectures

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  1. http://www.cdrinfo.com/Sections/News/Details.aspx?NewsId=49153
  2. http://www.cdrinfo.com/Sections/News/Details.aspx?NewsId=49153
  3. http://www.cdrinfo.com/Sections/News/Details.aspx?NewsId=49153