Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "280 nm lithography process"
(→Industry) |
|||
| Line 3: | Line 3: | ||
== Industry == | == Industry == | ||
| + | Around 1996 Intel introduced a stopgap shrink between [[0.35 µm]] and [[0.35 µm]], the process was used in Intel's {{intel|Klamath|l=core}} {{intel|P6|l=arch}} core. | ||
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Process Name | |Process Name | ||
| Line 15: | Line 16: | ||
! [[Intel]] || [[Motorola]] | ! [[Intel]] || [[Motorola]] | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | | || HiPerMOS 3 | + | | P854.5? || HiPerMOS 3 |
|- | |- | ||
| 1996 || 1997 | | 1996 || 1997 | ||
Revision as of 19:22, 30 March 2017
Semiconductor lithography processes technology
The 280 nanometer (280 nm) lithography process is was semiconductor manufacturing process following the 350 nm process. Commercial integrated circuit manufacturing using 280 nm process began in late 1990s. 280 nm and was phased out and later replaced by 250 nm, 220 nm, and 180 nm processes.
Industry
Around 1996 Intel introduced a stopgap shrink between 0.35 µm and 0.35 µm, the process was used in Intel's Klamath P6 core.
| Fab |
|---|
| Process Name |
| 1st Production |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| Metal Layers |
| SRAM bit cell |
280 nm Microprocessors
This list is incomplete; you can help by expanding it.
280 nm Microarchitectures
- Intel P6
This list is incomplete; you can help by expanding it.