From WikiChip
Difference between revisions of "16 µm lithography process"

Line 1: Line 1:
 
{{lithography processes}}
 
{{lithography processes}}
−
The '''16 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the late 1960s. This process had an effective channel length of roughly 16 µm between the source and drain (Poly-SI channel implant). The typical [[wafer]] size for this process at companies such as [[Fairchild]] was 1.25 inch (32 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages.
+
The '''16 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the late 1960s. This process had an effective channel length of roughly 16 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this process was 1.1-inch (28 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages.
  
  

Revision as of 12:03, 22 January 2017

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 16 µm lithography process was the semiconductor process technology used by semiconductor companies during the late 1960s. This process had an effective channel length of roughly 16 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process was 1.1-inch (28 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages.


Text document with shapes.svg This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information.
Retrieved from "https://en.wikichip.org/w/index.php?title=16_µm_lithography_process&oldid=38263"