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Difference between revisions of "90 nm lithography process"

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! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Fujitsu]] || colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] / [[Chartered]]
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! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Fujitsu]] || colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] / [[Chartered]] !! colspan="2" | [[Motorola]]
 
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| colspan="2" | P1262 || colspan="2" |  || colspan="2" |  || colspan="2" | CS-100 / CS-101 || colspan="2" |   
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| colspan="2" | P1262 || colspan="2" |  || colspan="2" |  || colspan="2" | CS-100 / CS-101 || colspan="2" |  || colspan="2" |  HiPerMOS 8
 
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| colspan="2" | 2002 || colspan="2" | 2003 || colspan="2" | 2003 || colspan="2" | 2004 || colspan="2" | 2003
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| colspan="2" | 2002 || colspan="2" | 2003 || colspan="2" | 2003 || colspan="2" | 2004 || colspan="2" | 2003 || colspan="2" | 2004
 
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| colspan="8" | Bulk || colspan="2" | PDSOI
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| colspan="8" | Bulk || colspan="4" | PDSOI
 
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| colspan="10" | 300mm
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| colspan="12" | 300mm
 
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! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ
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! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ !! Value !! [[130 nm]] Δ
 
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| 260 nm || 0.82x || 240 nm || 0.77x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x
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| 260 nm || 0.82x || 240 nm || 0.77x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 
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| 220 nm || 0.63x || 240 nm || 0.71x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x
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| 220 nm || 0.63x || 240 nm || 0.71x || 245 nm || 0.70x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 
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| 1.0 µm<sup>2</sup> || 0.50x || 0.999 µm<sup>2</sup> || 0.47x ||  0.999 µm<sup>2</sup> || ?x || 1.07 µm<sup>2</sup> || 0.54x || 0.999 µm<sup>2</sup> || ?x
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| 1.0 µm<sup>2</sup> || 0.50x || 0.999 µm<sup>2</sup> || 0.47x ||  0.999 µm<sup>2</sup> || ?x || 1.07 µm<sup>2</sup> || 0.54x || 0.999 µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x
 
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| || || || || || || || || 0.19 µm<sup>2</sup> || ?x
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| || || || || || || || || 0.19 µm<sup>2</sup> || ?x || ||
 
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Revision as of 00:22, 27 April 2016

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 90 nm lithography process is a full node semiconductor manufacturing process following the 110 nm process stopgap. Commercial integrated circuit manufacturing using 90 nm process began in 2003. This technology was superseded by the 80 nm process (HN) / 65 nm process (FN) in 2006.

Industry

Fab
Process Name​
1st Production​
Type​
Wafer​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell​
DRAM bit cell
Intel TSMC Samsung Fujitsu IBM / Toshiba / Sony / AMD / Chartered Motorola
P1262 CS-100 / CS-101 HiPerMOS 8
2002 2003 2003 2004 2003 2004
Bulk PDSOI
300mm
Value 130 nm Δ Value 130 nm Δ Value 130 nm Δ Value 130 nm Δ Value 130 nm Δ Value 130 nm Δ
260 nm 0.82x 240 nm 0.77x 245 nm 0.70x  ? nm  ?x  ? nm  ?x  ? nm  ?x
220 nm 0.63x 240 nm 0.71x 245 nm 0.70x  ? nm  ?x  ? nm  ?x  ? nm  ?x
1.0 µm2 0.50x 0.999 µm2 0.47x 0.999 µm2  ?x 1.07 µm2 0.54x 0.999 µm2  ?x  ? µm2  ?x
0.19 µm2  ?x

90 nm Microprocessors

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90 nm System on Chips

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90 nm Microarchitectures

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