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Difference between revisions of "3 µm lithography process"
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| process 1 delta from = N/A | | process 1 delta from = N/A | ||
− | | process 1 gate len = 3 | + | | process 1 gate len = 3 µm |
| process 1 gate len Δ = - | | process 1 gate len Δ = - | ||
| process 1 cpp = | | process 1 cpp = |
Revision as of 01:02, 6 May 2017
The 3 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s.
Industry
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Metal Layers | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Hitachi | |
---|---|
Hi-CMOS I | |
1978 | |
Bulk | |
Planar | |
5 V | |
1 | |
Value | N/A |
3 µm | N/A |
896 µm² | |
3 μm Microprocessors
- Intel
- Novix NC4016
- Dec
- Siemens
- Fairchild
- Toshiba
- National
- ARM
This list is incomplete; you can help by expanding it.
3 μm Microcontrollers
3 μm Chips
References
- Hitachi
- Sakai, Yoshio, et al. "High packing density, high speed CMOS (Hi-CMOS) device technology." Japanese Journal of Applied Physics 18.S1 (1979): 73.
- Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
- Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.