Semiconductor & Computer Engineering
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Difference between revisions of "22 nm lithography process"
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|Fin Width | |Fin Width | ||
|Fin Height | |Fin Height | ||
| + | |Gate Length | ||
|Contacted Gate Pitch | |Contacted Gate Pitch | ||
|Interconnect Pitch (M1P) | |Interconnect Pitch (M1P) | ||
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! Value !! [[32 nm]] Δ !! Value !! [[32 nm]] Δ !! Value !! [[32 nm]] Δ | ! Value !! [[32 nm]] Δ !! Value !! [[32 nm]] Δ !! Value !! [[32 nm]] Δ | ||
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| − | | 60 nm || rowspan="3" style="text-align: center;" | N/A || 45 nm || rowspan=" | + | | 60 nm || rowspan="3" style="text-align: center;" | N/A || 45 nm || rowspan="9" style="text-align: center;" | N/A || colspan="2" rowspan="3" style="text-align: center;" | N/A |
|- | |- | ||
| 8 nm || ? nm | | 8 nm || ? nm | ||
|- | |- | ||
| 34 nm || ? nm | | 34 nm || ? nm | ||
| + | |- | ||
| + | | 26 nm || || 30 nm || || | ||
|- | |- | ||
| 90 nm || 0.80x || 108 nm || 100 nm || 0.79x | | 90 nm || 0.80x || 108 nm || 100 nm || 0.79x | ||
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== References == | == References == | ||
* Narasimha, S., et al. "22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL." Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012. | * Narasimha, S., et al. "22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL." Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012. | ||
| + | * Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. | ||
[[Category:Lithography]] | [[Category:Lithography]] | ||
Revision as of 07:01, 4 April 2017
Semiconductor lithography processes technology
The 22 nanometer (22 nm) lithography process is a full node semiconductor manufacturing process following the 28 nm process stopgap. The term "22 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 22 nm process began in 2008 for memory and 2012 for MPUs. This technology was replaced by with 20 nm process (HN) in 2014 and 16 nm process (FN) in late 2015.
Contents
Industry
The 22 nm became Intel's first generation of Tri-gate FinFET transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom foundry.
| Fab |
|---|
| Process Name |
| 1st Production |
| Transistor |
| Wafer |
| |
| Fin Pitch |
| Fin Width |
| Fin Height |
| Gate Length |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HP) |
| SRAM bit cell (HD) |
| DRAM bit cell |
| Intel | Common Platform | ||||||
|---|---|---|---|---|---|---|---|
| P1270 (CPU) / P1271 (SoC) | 22FFL | ||||||
| FinFET | Planar | ||||||
| 2011 | 2017 | 2012 | |||||
| 300 mm | |||||||
| Value | 32 nm Δ | Value | 32 nm Δ | Value | 32 nm Δ | ||
| 60 nm | N/A | 45 nm | N/A | N/A | |||
| 8 nm | ? nm | ||||||
| 34 nm | ? nm | ||||||
| 26 nm | 30 nm | ||||||
| 90 nm | 0.80x | 108 nm | 100 nm | 0.79x | |||
| 80 nm | 0.71x | 90 nm | 80 nm | ?x | |||
| 0.1080 µm² | 0.63x | ? µm² | 0.1 µm² | 0.67x | |||
| 0.092 µm² | ?x | 0.88 µm² | ? µm² | ?x | |||
| 0.026 µm² | 0.67x | ||||||
Intel
| Intel 22nm SoC Interconnect Design Rules | ||||||
|---|---|---|---|---|---|---|
| Layer | Pitch | Process | Dielectric Materials | CPU | SoC | Image |
| Fin | 60 nm | - | - | Fin | Fin | 
|
| Contact | 90 nm | SAC | - | Contact | Contact | |
| M1 | 90 nm | SAV | ULK CDO | M1 | M1 | |
| MT - 1x | 80 nm | SAV | ULK CDO | M2/M3 | 2-6 layers | |
| MT - 1.4x | 112 nm | SAV | ULK CDO | M4 | Semi-global | |
| MT - 2x | 160 nm | SAV | ULK CDO | M5 | Semi-global | |
| MT - 3x | 240 nm | SAV | ULK CDO | M6 | Global Routing | |
| MT - 4x | 320 nm 360 nm |
Via First | LK CDO | M7/M8 | Global Routing | |
| MT - TOP | 14 µm | Plate Up | Polymer | M9 | Top Metal | |
| Intel 22nm SoC Transistor Characteristics | ||||||
|---|---|---|---|---|---|---|
| Transistor Type | High Speed Logic | Low Power Logic | High Voltage Logic | |||
| Options | High Performance (HP) | Standard Perf/Power (SP) | Low Power (LP) | Ultra-Low Power (ULP) | 1.8 V | 3.3 V |
| Vdd (V) | 0.75 V / 1 V | 0.75 V / 1 V | 0.75 V / 1 V | 0.75 V / 1.2 V | 1.5 V / 1.8 V / 3.3 V | 3.3 V / >5V |
| Gate Pitch (nm) | 90 | 90 | 90 | 108 | min. 180 | min 450 |
| Lgate (nm) | 30 | 34 | 34 | 40 | min. 80 | in 280 |
| N/PMOS Idsat/Ioff (mA/µm) | 1.08/0.91 @ 0.75 V, 100 nA/µm | 0.71/0.59 @0.75 V, 1 nA/µm | 0.41/0.37 @ 0.75 V, 30 pA/µm | 0.35/0.33 @ 0.75 V, 15 pA/µm | 0.92/0.8 @ 1.8 V, 10 pA/µm | 1/0.8 @ 3.3 V, 10 pA/µm |
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22 nm Microprocessors
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22 nm Microarchitectures
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Documents
References
- Narasimha, S., et al. "22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL." Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012.
- Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.