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Difference between revisions of "20 µm lithography process"

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{{lithography processes}}
 
{{lithography processes}}
The '''20 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the mid to late 1960s. 20 µm was roughly the pitch between the centers of two smallest-sized transistors. The typical [[wafer]] size for this process at companies such as [[Fairchild]] was 0.875 inch (22 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages.
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The '''20 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the mid to late 1960s. 20 µm was roughly the pitch between the centers of two smallest-sized transistors. The typical [[wafer]] size for this process was 0.875 inch (22 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages and dual in-line packages.
  
 
== Industry ==
 
== Industry ==

Revision as of 07:38, 27 April 2016

The 20 µm lithography process was the semiconductor process technology used by semiconductor companies during the mid to late 1960s. 20 µm was roughly the pitch between the centers of two smallest-sized transistors. The typical wafer size for this process was 0.875 inch (22 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages and dual in-line packages.

Industry

Fab
1st Production​
Contacted Gate Pitch​
Interconnect Pitch​
Technology
RCA
1968
 ? nm
 ? nm
CMOS

20 µm Chips

  • RCA

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