Semiconductor & Computer Engineering
| Line 68: | Line 68: | ||
* Intel | * Intel | ||
** {{intel|Core i7EE}} | ** {{intel|Core i7EE}} | ||
| + | {{expand list}} | ||
| − | |||
| + | {{#ask: | ||
| + | [[instance of::microprocessor]] | ||
| + | [[process::14 nm]] | ||
| + | | ?name | ||
| + | | ?process | ||
| + | | ?manufacturer | ||
| + | | ?microprocessor family | ||
| + | | format=broadtable | ||
| + | | limit=0 | ||
| + | | sep=, | ||
| + | | searchlabel=Click to browse all 14 nm MPU models | ||
| + | }} | ||
== 14 nm System on Chips== | == 14 nm System on Chips== | ||
* Intel | * Intel | ||
| Line 76: | Line 88: | ||
** {{intel|Atom x7}} | ** {{intel|Atom x7}} | ||
** {{intel|Xeon D}} | ** {{intel|Xeon D}} | ||
| − | |||
{{expand list}} | {{expand list}} | ||
| Line 85: | Line 96: | ||
** {{intel|Broadwell}} | ** {{intel|Broadwell}} | ||
** {{intel|Skylake}} | ** {{intel|Skylake}} | ||
| + | {{expand list}} | ||
== Documents == | == Documents == | ||
* [http://www.intel.com/content/dam/www/public/us/en/documents/pdf/foundry/intel-14nm-iedm-2014-presentation.pdf A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size], 15-17 Dec. 2014; 10.1109/IEDM.2014.7046976 | * [http://www.intel.com/content/dam/www/public/us/en/documents/pdf/foundry/intel-14nm-iedm-2014-presentation.pdf A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size], 15-17 Dec. 2014; 10.1109/IEDM.2014.7046976 | ||
| − | |||
[[Category:Lithography]] | [[Category:Lithography]] | ||
Revision as of 03:09, 26 April 2016
Semiconductor lithography processes technology
The 14 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 16 nm and 10 nm processes. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 14 nm process began in 2014. This technology is set to be replaced with 10 nm process in 2017.
Contents
Industry
14 nm became Intel's 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals.
| Fab |
|---|
| Process Name |
| 1st Production |
| Type |
| |
| Fin Pitch |
| Fin Width |
| Fin Height |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HP) |
| SRAM bit cell (HD) |
| DRAM bit cell |
| Intel | Samsung | GlobalFoundries | IBM | ||||
|---|---|---|---|---|---|---|---|
| P1272 | |||||||
| 2014 | 2015 | 2015 | 2015 | ||||
| Bulk | PDSOI | ||||||
| Value | 22 nm Δ | Value | 20 nm Δ | Value | 20 nm Δ | Value | 22 nm Δ |
| 42 nm | 0.70x | 48 nm | N/A | 48 nm | N/A | 42 nm | N/A |
| 8 nm | 1.00x | 8 nm | 8 nm | 10 nm | |||
| 42 nm | 1.24x | ~38 nm | ~38 nm | 25 nm | |||
| 70 nm | 0.78x | 78 nm | 1.22x | 78 nm | 1.22x | 80 nm | 0.80x |
| 52 nm | 0.65x | 64 nm | 1.00x | 64 nm | 1.00x | 64 nm | 0.80x |
| 0.0588 µm2 | 0.54x | 0.08 µm2 | ?x | 0.08 µm2 | ?x | ? µm2 | ?x |
| 0.064 µm2 | ?x | 0.064 µm2 | ?x | ? µm2 | ?x | ||
| 0.0174 µm2 | 0.67x | ||||||
Design Rules
| Intel 14nm Design Rules | ||
|---|---|---|
| Layer | Pitch | Scale Factor |
| Fin | 42 nm | 0.70 |
| Contacted Gate Pitch | 70 nm | 0.78 |
| Metal 0 | 56 | - |
| Metal 1 | 70 | 0.78 |
| Metal 2 | 52 | 0.65 |
14 nm Microprocessors
- Intel
This list is incomplete; you can help by expanding it.
Click to browse all 14 nm MPU models
14 nm System on Chips
This list is incomplete; you can help by expanding it.
14 nm Microarchitectures
This list is incomplete; you can help by expanding it.
Documents
- A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size, 15-17 Dec. 2014; 10.1109/IEDM.2014.7046976