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Difference between revisions of "16 µm lithography process"

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{{lithography processes}}
 
{{lithography processes}}
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The '''16 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1965 and 1968. The typical [[wafer]] size for this process at companies such as [[Fairchild]] was 1.25 inch (32 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages.
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The '''16 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the late 1960s. The typical [[wafer]] size for this process at companies such as [[Fairchild]] was 1.25 inch (32 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages.
  
  

Revision as of 01:49, 26 April 2016

basic wafer drawing.svg Semiconductor lithography processes technology
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The 16 µm lithography process was the semiconductor process technology used by semiconductor companies during the late 1960s. The typical wafer size for this process at companies such as Fairchild was 1.25 inch (32 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages.


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