From WikiChip
Difference between revisions of "3 µm lithography process"

m (Bot: Automated text replacement (-Category:Lithography +category:lithography))
 
(15 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
{{Lithography processes}}
 
{{Lithography processes}}
−
The '''3μm lithography process''' was the semiconductor process technology used by some semiconductor companies during from 1978 to 1985.
+
The '''3 μm lithography process''' was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s.
  
−
== Microprocessors ==
+
== Industry ==
 +
 
 +
{{nodes comp
 +
<!-- Hitachi -->
 +
| process 1 fab          = [[Hitachi]]
 +
| process 1 name        = Hi-CMOS I
 +
| process 1 date        = 1978
 +
| process 1 lith        = &nbsp;
 +
| process 1 immersion    = &nbsp;
 +
| process 1 exposure    = &nbsp;
 +
| process 1 wafer type  = Bulk
 +
| process 1 wafer size  = &nbsp;
 +
| process 1 transistor  = Planar
 +
| process 1 volt        = 5 V
 +
| process 1 layers      = 1
 +
| process 1 delta from  = N/A
 +
| process 1 gate len    = 3 µm
 +
| process 1 gate len Δ  = -
 +
| process 1 cpp          = &nbsp;
 +
| process 1 cpp Δ        = -
 +
| process 1 mmp          = &nbsp;
 +
| process 1 mmp Δ        = -
 +
| process 1 sram hp      = &nbsp;
 +
| process 1 sram hp Δ    = -
 +
| process 1 sram hd      = 896 µm²
 +
| process 1 sram hd Δ    = -
 +
| process 1 sram lv      = &nbsp;
 +
| process 1 sram lv Δ    = -
 +
| process 1 dram        = &nbsp;
 +
| process 1 dram Δ      = -
 +
 
 +
<!-- VLSI Technology -->
 +
| process 2 fab          = [[VLSI Technology]]
 +
| process 2 name        = &nbsp;
 +
| process 2 date        = &nbsp;
 +
| process 2 lith        = &nbsp;
 +
| process 2 immersion    = &nbsp;
 +
| process 2 exposure    = &nbsp;
 +
| process 2 wafer type  = Bulk
 +
| process 2 wafer size  = &nbsp;
 +
| process 2 transistor  = Planar
 +
| process 2 volt        = 5 V
 +
| process 2 layers      = 2
 +
| process 2 delta from  = N/A
 +
| process 2 gate len    = 3 µm
 +
| process 2 gate len Δ  = -
 +
| process 2 cpp          = &nbsp;
 +
| process 2 cpp Δ        = -
 +
| process 2 mmp          = &nbsp;
 +
| process 2 mmp Δ        = -
 +
| process 2 sram hp      = &nbsp;
 +
| process 2 sram hp Δ    = -
 +
| process 2 sram hd      = &nbsp;
 +
| process 2 sram hd Δ    = -
 +
| process 2 sram lv      = &nbsp;
 +
| process 2 sram lv Δ    = -
 +
| process 2 dram        = &nbsp;
 +
| process 2 dram Δ      = -
 +
}}
 +
 
 +
== 3 μm Microprocessors ==
 
* Intel
 
* Intel
 +
** {{intel|8085}}
 
** {{intel|8086}}
 
** {{intel|8086}}
 
** {{intel|8088}}
 
** {{intel|8088}}
Line 9: Line 70:
 
* [[Novix NC4016]]
 
* [[Novix NC4016]]
 
* Dec
 
* Dec
−
** {{dec|MicroVAX 78032}}
+
** {{decc|MicroVAX 78032}}
 +
* Siemens
 +
** {{siemens|SAB 80199}}
 +
* Fairchild
 +
** {{fairchild|6800}}
 +
* Toshiba
 +
** {{toshiba|8085}}
 +
* National
 +
** {{national|COPS II}}
 +
* ARM
 +
** {{armh|ARM1|l=arch}}
 +
{{expand list}}
 +
 
 +
== 3 μm Microcontrollers ==
 +
* Intel
 +
** {{intel|MCS-41}}
 +
** {{intel|MCS-48}}
 +
** {{intel|MCS-51}}
 +
 
 +
== 3 μm Chips ==
 +
* Intel
 +
** {{intel|8087}}
 +
** {{intel|8089}}
 +
** {{intel|8220}}
 +
* National
 +
** {{national|32081}}
 +
* AMD
 +
** {{amd|2901}}
  
−
{{stub}}
+
== References ==
 +
* Hitachi
 +
** Sakai, Yoshio, et al. "High packing density, high speed CMOS (Hi-CMOS) device technology." Japanese Journal of Applied Physics 18.S1 (1979): 73.
 +
** Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
 +
** Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.
  
−
[[Category:Lithography]]
+
[[category:lithography]]

Latest revision as of 22:04, 20 May 2018

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 3 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s.

Industry[edit]

 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Hitachi VLSI Technology
Hi-CMOS I  
1978  
   
   
   
Bulk Bulk
   
Planar Planar
5 V 5 V
1 2
Value N/A Value N/A
3 µm N/A 3 µm N/A
   
   
   
896 µm²  
   
   

3 μm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

3 μm Microcontrollers[edit]

3 μm Chips[edit]

References[edit]

  • Hitachi
    • Sakai, Yoshio, et al. "High packing density, high speed CMOS (Hi-CMOS) device technology." Japanese Journal of Applied Physics 18.S1 (1979): 73.
    • Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
    • Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.
Retrieved from "https://en.wikichip.org/w/index.php?title=3_µm_lithography_process&oldid=77998"