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| process 2 fab = [[TSMC]] | | process 2 fab = [[TSMC]] | ||
− | | process 2 name = | + | | process 2 name = N3, N3E <info>N3 Enhanced</info> |
− | | process 2 date = | + | | process 2 date = 2H 2022 |
| process 2 lith = EUV | | process 2 lith = EUV | ||
| process 2 immersion = | | process 2 immersion = |
Revision as of 16:49, 17 November 2021
The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.
Industry
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Intel | TSMC | Samsung | |||
---|---|---|---|---|---|
P1280? (CPU), P1281? (SoC) | N3, N3E N3 Enhanced |
3GAE 3nm Gate All Around Early , 3GAP3nm Gate All Around Plus
| |||
2H 2022 | |||||
EUV | EUV | EUV | |||
SE | SE | SE | |||
Bulk | Bulk | Bulk | |||
300 mm | 300 mm | 300 mm | |||
FinFET | GAA | ||||
Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ |
N/A | |||||
Samsung
On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.
3 nm Microprocessors
This list is incomplete; you can help by expanding it.
3 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017