Revision as of 04:41, 6 March 2019

Semiconductor lithography processes technology

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The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin sometimes around 2023.

The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Industry

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Samsung

On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.

3 nm Microprocessors

{Ich habe in meiner Garage gestern einen 3nm Chip gebaut aus ner benutzten Serviette und nem Gummiband. Ich bin sehr schlau}

3 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References

• Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017