Semiconductor & Computer Engineering
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== Industry == | == Industry == | ||
| − | Around 1996 Intel introduced a stopgap shrink between [[0.35 µm]] and [[0.25 µm]]. Unlike [[0.35 µm]] which used BiCMOS process for their {{intel|Pentium}} and {{intel|Pentium Pro}} processors, the 0.28 µm process was a standard CMOS process. The process was used in Intel's {{intel|P55C}} and | + | Around 1996 Intel introduced a stopgap shrink between [[0.35 µm]] and [[0.25 µm]]. Unlike [[0.35 µm]] which used BiCMOS process for their {{intel|Pentium}} and {{intel|Pentium Pro}} processors, the 0.28 µm process was a standard CMOS process. Featuring a smaller transistor gate pitch, the process shared similar metal layer sizes to the [[0.35 µm]] (this is why some Intel documents refer to it as "0.35µm"). The process was used in Intel's {{intel|P55C}} ({{x86|MMX}}) and {{intel|P6|l=arch}} {{intel|Klamath|l=core}} core-based and models. The semi-shrink which resulted in smaller transistors and improved switching speed was done to compensate for the return to CMOS (i.e., lack of fast bipolar transistors). |
| − | {{intel|P6|l=arch}} {{intel|Klamath|l=core}} core-based and models. The semi-shrink which resulted in smaller transistors and improved switching speed was done to compensate for the return to CMOS (i.e., lack of fast bipolar transistors). | ||
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Process Name | |Process Name | ||
|1st Production | |1st Production | ||
| + | |Voltage | ||
|Contacted Gate Pitch | |Contacted Gate Pitch | ||
|Interconnect Pitch (M1P) | |Interconnect Pitch (M1P) | ||
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|- | |- | ||
| 1996 || 1997 | | 1996 || 1997 | ||
| + | |- | ||
| + | | 2.8 V || ? V | ||
|- | |- | ||
| ? nm || ? nm | | ? nm || ? nm | ||
|- | |- | ||
| − | | | + | | 880 nm || ? nm |
|- | |- | ||
| 4 || ? | | 4 || ? | ||
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* Intel {{intel|P6|l=arch}} | * Intel {{intel|P6|l=arch}} | ||
{{expand list}} | {{expand list}} | ||
| + | |||
| + | [[category:lithography]] | ||
Latest revision as of 05:11, 20 July 2018
Semiconductor lithography processes technology
The 280 nanometer (280 nm) lithography process is was semiconductor manufacturing process following the 350 nm process. Commercial integrated circuit manufacturing using 280 nm process began in late 1990s. 280 nm and was phased out and later replaced by 250 nm, 220 nm, and 180 nm processes.
Industry[edit]
Around 1996 Intel introduced a stopgap shrink between 0.35 µm and 0.25 µm. Unlike 0.35 µm which used BiCMOS process for their Pentium and Pentium Pro processors, the 0.28 µm process was a standard CMOS process. Featuring a smaller transistor gate pitch, the process shared similar metal layer sizes to the 0.35 µm (this is why some Intel documents refer to it as "0.35µm"). The process was used in Intel's P55C (MMX) and P6 Klamath core-based and models. The semi-shrink which resulted in smaller transistors and improved switching speed was done to compensate for the return to CMOS (i.e., lack of fast bipolar transistors).
| Fab |
|---|
| Process Name |
| 1st Production |
| Voltage |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| Metal Layers |
| SRAM bit cell |
280 nm Microprocessors[edit]
This list is incomplete; you can help by expanding it.
280 nm Microarchitectures[edit]
- Intel P6
This list is incomplete; you can help by expanding it.