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Difference between revisions of "3 µm lithography process"
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| process 1 layers = 1 | | process 1 layers = 1 | ||
| process 1 delta from = N/A | | process 1 delta from = N/A | ||
| − | | process 1 gate len = 3 | + | | process 1 gate len = 3 µm |
| process 1 gate len Δ = - | | process 1 gate len Δ = - | ||
| process 1 cpp = | | process 1 cpp = | ||
| Line 32: | Line 32: | ||
| process 1 dram = | | process 1 dram = | ||
| process 1 dram Δ = - | | process 1 dram Δ = - | ||
| + | |||
| + | <!-- VLSI Technology --> | ||
| + | | process 2 fab = [[VLSI Technology]] | ||
| + | | process 2 name = | ||
| + | | process 2 date = | ||
| + | | process 2 lith = | ||
| + | | process 2 immersion = | ||
| + | | process 2 exposure = | ||
| + | | process 2 wafer type = Bulk | ||
| + | | process 2 wafer size = | ||
| + | | process 2 transistor = Planar | ||
| + | | process 2 volt = 5 V | ||
| + | | process 2 layers = 2 | ||
| + | | process 2 delta from = N/A | ||
| + | | process 2 gate len = 3 µm | ||
| + | | process 2 gate len Δ = - | ||
| + | | process 2 cpp = | ||
| + | | process 2 cpp Δ = - | ||
| + | | process 2 mmp = | ||
| + | | process 2 mmp Δ = - | ||
| + | | process 2 sram hp = | ||
| + | | process 2 sram hp Δ = - | ||
| + | | process 2 sram hd = | ||
| + | | process 2 sram hd Δ = - | ||
| + | | process 2 sram lv = | ||
| + | | process 2 sram lv Δ = - | ||
| + | | process 2 dram = | ||
| + | | process 2 dram Δ = - | ||
}} | }} | ||
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** Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984. | ** Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984. | ||
| − | [[ | + | [[category:lithography]] |
Latest revision as of 22:04, 20 May 2018
Semiconductor lithography processes technology
The 3 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s.
Industry[edit]
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Metal Layers | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Hitachi | VLSI Technology | ||
|---|---|---|---|
| Hi-CMOS I | |||
| 1978 | |||
| Bulk | Bulk | ||
| Planar | Planar | ||
| 5 V | 5 V | ||
| 1 | 2 | ||
| Value | N/A | Value | N/A |
| 3 µm | N/A | 3 µm | N/A |
| 896 µm² | |||
3 μm Microprocessors[edit]
- Intel
- Novix NC4016
- Dec
- Siemens
- Fairchild
- Toshiba
- National
- ARM
This list is incomplete; you can help by expanding it.
3 μm Microcontrollers[edit]
3 μm Chips[edit]
References[edit]
- Hitachi
- Sakai, Yoshio, et al. "High packing density, high speed CMOS (Hi-CMOS) device technology." Japanese Journal of Applied Physics 18.S1 (1979): 73.
- Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
- Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.