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Difference between revisions of "3 µm lithography process"

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== Industry ==
 
== Industry ==
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{{scrolling table/top|style=text-align: right; | first=Fab
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  |Process Name
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{{nodes comp
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  |1st Production
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<!-- Hitachi -->
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  |Voltage
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| process 1 fab          = [[Hitachi]]
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  |&nbsp;
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| process 1 name        = Hi-CMOS I
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  |Gate Length
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| process 1 date        = 1978
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  |Interconnect Pitch (M1P)
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| process 1 lith        = &nbsp;
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  |SRAM bit cell
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| process 1 immersion    = &nbsp;
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| process 1 exposure    = &nbsp;
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| process 1 wafer type  = Bulk
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| process 1 wafer size  = &nbsp;
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| process 1 transistor  = Planar
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| process 1 volt        = 5 V
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| process 1 layers      = 1
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| process 1 delta from  = N/A
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| process 1 gate len    = 3 µm
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| process 1 gate len Δ  = -
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| process 1 cpp          = &nbsp;
 +
| process 1 cpp Δ        = -
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| process 1 mmp          = &nbsp;
 +
| process 1 mmp Δ        = -
 +
  | process 1 sram hp      = &nbsp;
 +
  | process 1 sram hp Δ    = -
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  | process 1 sram hd      = 896 µm²
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  | process 1 sram hd Δ    = -
 +
| process 1 sram lv      = &nbsp;
 +
  | process 1 sram lv Δ    = -
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  | process 1 dram        = &nbsp;
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  | process 1 dram Δ      = -
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<!-- VLSI Technology -->
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| process 2 fab          = [[VLSI Technology]]
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| process 2 name        = &nbsp;
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| process 2 date        = &nbsp;
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| process 2 lith        = &nbsp;
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| process 2 immersion    = &nbsp;
 +
| process 2 exposure    = &nbsp;
 +
| process 2 wafer type  = Bulk
 +
| process 2 wafer size  = &nbsp;
 +
| process 2 transistor  = Planar
 +
| process 2 volt        = 5 V
 +
| process 2 layers      = 2
 +
| process 2 delta from  = N/A
 +
| process 2 gate len    = 3 µm
 +
| process 2 gate len Δ  = -
 +
| process 2 cpp          = &nbsp;
 +
| process 2 cpp Δ        = -
 +
| process 2 mmp          = &nbsp;
 +
| process 2 mmp Δ        = -
 +
| process 2 sram hp      = &nbsp;
 +
| process 2 sram hp Δ    = -
 +
| process 2 sram hd      = &nbsp;
 +
| process 2 sram hd Δ    = -
 +
| process 2 sram lv      = &nbsp;
 +
| process 2 sram lv Δ    = -
 +
| process 2 dram        = &nbsp;
 +
| process 2 dram Δ      = -
 
}}
 
}}
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{{scrolling table/mid}}
 
−
|-
 
−
! [[Hitachi]]
 
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|- style="text-align: center;"
 
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|  Hi-CMOS I
 
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|- style="text-align: center;"
 
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| ?
 
−
|-
 
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| 5 V
 
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|-
 
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! Value
 
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|-
 
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| 3 µm
 
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|-
 
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| 3 µm
 
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|-
 
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| 896 µm²
 
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{{scrolling table/end}}
 
  
 
== 3 μm Microprocessors ==
 
== 3 μm Microprocessors ==
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== References ==
 
== References ==
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* Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
+
* Hitachi
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* Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.
+
** Sakai, Yoshio, et al. "High packing density, high speed CMOS (Hi-CMOS) device technology." Japanese Journal of Applied Physics 18.S1 (1979): 73.
 +
** Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
 +
** Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.
  
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[[Category:Lithography]]
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[[category:lithography]]

Latest revision as of 22:04, 20 May 2018

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 3 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s.

Industry[edit]

 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Hitachi VLSI Technology
Hi-CMOS I  
1978  
   
   
   
Bulk Bulk
   
Planar Planar
5 V 5 V
1 2
Value N/A Value N/A
3 µm N/A 3 µm N/A
   
   
   
896 µm²  
   
   

3 μm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

3 μm Microcontrollers[edit]

3 μm Chips[edit]

References[edit]

  • Hitachi
    • Sakai, Yoshio, et al. "High packing density, high speed CMOS (Hi-CMOS) device technology." Japanese Journal of Applied Physics 18.S1 (1979): 73.
    • Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
    • Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.
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