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Difference between revisions of "3.5 µm lithography process"
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{{Lithography processes}} | {{Lithography processes}} | ||
− | The '''3.5 μm lithography process''' was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process was later superseded by [[3 µm]], [[2 µm]], and [[1.5 µm]] processes. | + | The '''3.5 μm lithography process''' was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process had an effective channel length of roughly 3.5 µm between the source and drain. This process was later superseded by [[3 µm]], [[2 µm]], and [[1.5 µm]] processes. |
== Industry == | == Industry == | ||
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{{scrolling table/mid}} | {{scrolling table/mid}} | ||
|- | |- | ||
− | ! [[Motorola]] | + | ! [[Intel]] || [[Motorola]] |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | | + | | HMOS-I || |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | | + | | 1978 || |
|- | |- | ||
− | | ? nm | + | | ? nm || ? nm |
|- | |- | ||
− | | ? nm | + | | ? nm || ? nm |
|- | |- | ||
− | | ? | + | | ? || ? |
|- | |- | ||
− | | nMOS | + | | nMOS || nMOS |
|- | |- | ||
− | | ?" | + | | ?" || ?" |
{{scrolling table/end}} | {{scrolling table/end}} | ||
== 3.5 μm microcontrollers == | == 3.5 μm microcontrollers == | ||
+ | * Intel | ||
+ | ** {{intel|8051}} | ||
* Bell Labs | * Bell Labs | ||
** {{bell|BELLMAC-4}} | ** {{bell|BELLMAC-4}} |
Revision as of 15:17, 4 June 2016
The 3.5 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process had an effective channel length of roughly 3.5 µm between the source and drain. This process was later superseded by 3 µm, 2 µm, and 1.5 µm processes.
Industry
Fab |
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Process Name |
1st Production |
Contacted Gate Pitch |
Interconnect Pitch |
Metal Layers |
Technology |
Wafer |
3.5 μm microcontrollers
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