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Difference between revisions of "10 µm lithography process"
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Revision as of 05:36, 26 April 2016
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The 10 µm lithography process was the semiconductor process technology used by the major semiconductor companies during the years of 1967 and 1973. The typical wafer size for this process at companies such as Fairchild and TI were 1.5 inch (38 mm).
Industry
Fab |
---|
Process Name |
1st Production |
Contacted Gate Pitch |
Interconnect Pitch |
Metal Layers |
Technology |
Intel | TI | RCA | Fairchild |
---|---|---|---|
1970 | 1969 | 1969 | |
? nm | ? nm | ? nm | ? nm |
? nm | ? nm | ? nm | ? nm |
2 | 2 | 2 | 2 |
PMOS | PMOS | PMOS | PMOS |
10 µm Microprocessors
This list is incomplete; you can help by expanding it.
Click to browse all 10 µm models
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This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |