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Difference between revisions of "20 µm lithography process"

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{{lithography processes}}
 
{{lithography processes}}
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The '''20 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1963 and 1967. 20 µm was roughly the pitch between the centers of two smallest-sized transistors. The typical [[wafer]] size for this process at companies such as [[Fairchild]] was 0.875 inch (22 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages.
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The '''20 µm lithography process''' was the [[semiconductor process]] technology used by semiconductor companies during the early 1960s. 20 µm was roughly the pitch between the centers of two smallest-sized transistors. The typical [[wafer]] size for this process at companies such as [[Fairchild]] was 0.875 inch (22 mm). The standard transistor packages those years were the [[TO-5]] and [[TO-18]] (Transistor Outline) metal-can packages.
  
  

Revision as of 02:48, 26 April 2016

basic wafer drawing.svg Semiconductor lithography processes technology
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The 20 µm lithography process was the semiconductor process technology used by semiconductor companies during the early 1960s. 20 µm was roughly the pitch between the centers of two smallest-sized transistors. The typical wafer size for this process at companies such as Fairchild was 0.875 inch (22 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages.


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