Revision as of 03:58, 1 July 2024

Semiconductor lithography processes technology

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The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.

The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Industry

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

| process 1 date         = 1H 2022

P1278

Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H2024/2025 timeframe.

Samsung

On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.

TSMC

N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website). If this holds true we could see 300+ MT/mm2.

3 nm Microprocessors

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3 nm Microarchitectures

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References

• Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017