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- ...chitecture that has a [[datapath]] width or a highest [[operand]] width of 128 bits or 16 [[octet]]s. These architectures typically have a matching [[regi ...number of microarchitectures that introduced various extensions to handle 128-bit arithmetic in a more specialized way.593 bytes (81 words) - 09:51, 20 July 2018
Page text matches
- var %hash $calc(($xor(%hash,$calc(%hash /128)) * 9) % 4294967296)30 KB (5,149 words) - 01:46, 30 November 2018
- * '''-a''' - Modifier for -t switch, codepoints 128-255 are not encoded to UTF8 if no codepoint above 255 is found2 KB (366 words) - 22:53, 16 August 2022
- ...these last 2 methods do not strictly conform to -ta because they add ASCII 128-255 as single bytes even when codepoint 256+ is present. Also, the last met9 KB (1,432 words) - 18:47, 2 May 2023
- ;Change the color of 1 in the color palette to purple (128, 0, 128). //color 1 $rgb(128,0,128)2 KB (255 words) - 22:38, 3 May 2023
- |i1 || single byte signed integer || -128 to 127 |decimal || Holds signed 128-bit (16-byte) values representing 96-bit (12-byte) integer numbers. || +/-727 KB (3,608 words) - 11:41, 25 October 2018
- ;Change the color of 1 in the color palette to purple (128, 0, 128). //colour 1 $rgb(128,0,128)2 KB (255 words) - 19:13, 15 June 2017
- |pcie lanes=1284 KB (693 words) - 01:48, 2 April 2023
- |pcie lanes=1284 KB (666 words) - 01:48, 2 April 2023
- ...-greater that's a multiple of 64, whose UTF8 encoding ends with byte value 128. In these cases, $decode matches the final byte of the message as if it is ...could end with 0x00, or with text strings which could end with byte value 128.12 KB (1,991 words) - 09:37, 14 November 2022
- ...Parameter#4. Salt is interpreted in ANSI mode without encoding codepoints 128-255 to 2 bytes, and codepoint >255 is an invalid parameter. Warning: $encod ...length 8 if shorter. Parameter#4 is interpreted in ANSI mode, where ASCII 128-255 are not UTF-8 encoded into byte-pairs and codepoint > 255 are invalid.33 KB (5,484 words) - 04:32, 16 April 2023
- ...|| VPOPCNTB/VPOPCNTW || Parallel population count on 8/16-bit operands in 128/256/512-bit vector ...|| VPOPCNTD/VPOPCNTQ || Parallel population count on 32/64-bit operands in 128/256/512-bit vector3 KB (447 words) - 01:55, 14 March 2023
- ...: 8 bits can be used to represent 256 values. Code pages all use the first 128 values for ASCII, and then each code page adds the required characters for * 128 - SHIFTJIS_CHARSET10 KB (1,506 words) - 10:13, 17 February 2024
- * '''128''' - show the question icon ('q')6 KB (1,062 words) - 07:12, 1 February 2024
- ...tecture|60-bit]] - [[64-bit architecture|64-bit]] - [[128-bit architecture|128-bit]] - [[256-bit architecture|256-bit]] - [[512-bit architecture|512-bit]]2 KB (248 words) - 23:48, 28 October 2015
- ...arithmetic. 512 to 2,048 Words (10-bit ea) of program [[ROM]]. Additional 128 Words (10-bit ea) of pattern ROM. 32 to 160 digits (4-bit ea) of data [[RAM4 KB (400 words) - 19:05, 24 May 2016
- | {{\|COP310C}} || 512 B || 128 b || 4.098 kHz - 62.5 kHz || DIP24 || CMOS, extended temperature version of | {{\|COP311C}} || 512 B || 128 b || 4.098 kHz - 62.5 kHz || DIP16 || CMOS, extended temperature version of6 KB (685 words) - 22:49, 5 February 2016
- | package 5 = QFP15-128 | package 8 = TQFP15-1285 KB (620 words) - 21:04, 7 February 2016
- &= 128 + 32 + 8 + 4 + 2 + 0.25 + 0.125 \\7 KB (935 words) - 07:08, 2 December 2015
- ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB4 KB (404 words) - 16:22, 13 December 2017
- ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB3 KB (401 words) - 14:24, 12 February 2019
- ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB3 KB (399 words) - 16:22, 13 December 2017
- ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}. |l1i cache=128 KiB3 KB (400 words) - 16:22, 13 December 2017
- ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB3 KB (399 words) - 16:22, 13 December 2017
- ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB3 KB (386 words) - 09:14, 26 December 2017
- ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB3 KB (401 words) - 16:22, 13 December 2017
- ...cludes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. |l1i cache=128 KiB3 KB (397 words) - 16:22, 13 December 2017
- ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB3 KB (398 words) - 16:22, 13 December 2017
- ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB4 KB (406 words) - 16:22, 13 December 2017
- ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB4 KB (404 words) - 16:19, 13 December 2017
- ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB3 KB (401 words) - 16:19, 13 December 2017
- ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB3 KB (396 words) - 16:22, 13 December 2017
- ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB3 KB (391 words) - 16:22, 13 December 2017
- ...U includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. |l1i cache=128 KiB3 KB (399 words) - 16:27, 13 December 2017
- |l1 cache=128 KiB4 KB (596 words) - 16:15, 13 December 2017
- |l1 cache=128 KiB4 KB (596 words) - 16:15, 13 December 2017
- |l1 cache=128 KiB4 KB (627 words) - 16:17, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (627 words) - 16:20, 13 December 2017
- |l1 cache=128 KiB4 KB (640 words) - 02:21, 16 January 2019
- |l1 cache=128 KiB4 KB (650 words) - 02:21, 16 January 2019
- ...tegrated graphic processors with an additional L4$ of {{intel|crystal well|128 MB eDRAM}}.2 KB (300 words) - 19:39, 3 January 2016
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (407 words) - 16:22, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (401 words) - 16:22, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (395 words) - 16:22, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (424 words) - 16:22, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (405 words) - 16:22, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (460 words) - 15:03, 24 March 2019
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (409 words) - 16:19, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (454 words) - 18:17, 2 November 2019
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (409 words) - 16:19, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (415 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB4 KB (631 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (649 words) - 16:20, 13 December 2017
- |l1 cache=128 KiB3 KB (323 words) - 16:10, 13 December 2017
- * '''-a''' - modifier for -t and -b, codepoints 128-255 are not encoded to UTF8 if no codepoint above 255 is found3 KB (435 words) - 13:00, 11 May 2023
- | {{\|M35011}} || 24x10 || 240 || 4x4 || 128x64 || 128 || background composition | {{\|M35013}} || 24x10 || 240 || 4x4 || 62x64 || 128 || background composition4 KB (438 words) - 01:00, 19 May 2016
- | {{\|MC141540}} || 320 ([[CGA]]) || 10x24 || 10x16 || 128 || 4 selectable colors per row ...1543}} || 320 ([[CGA]]), 480 ([[EGA]]), 640 ([[VGA]]) || 15x30 || 10x16 || 128 || char-by-char coloring2 KB (200 words) - 01:00, 19 May 2016
- | {{\|MTV004}} || || 10x24 || 12x16 || 128 || | {{\|MTV016}} || up to 1524 || 10x24 || 12x18 || 128 ||1 KB (101 words) - 13:01, 12 February 2016
- ...capabilities. Models support up to dual-channel DDR4 ECC memory and either 128 GiB or 256 GiB of memory. All models support everything up to SSE4.2 (SMM,17 KB (2,292 words) - 09:32, 16 July 2019
- | Metal 3 || 128 nm * Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE17 KB (2,243 words) - 19:32, 25 May 2023
- |l1i cache=128 KiB4 KB (462 words) - 16:15, 13 December 2017
- |l1i cache=128 KiB4 KB (472 words) - 16:15, 13 December 2017
- |l1i cache=128 KiB4 KB (475 words) - 17:42, 27 March 2018
- |l1i cache=128 KiB5 KB (573 words) - 16:15, 13 December 2017
- |l1i cache=128 KiB5 KB (572 words) - 16:15, 13 December 2017
- |l1i cache=128 KiB6 KB (744 words) - 18:35, 14 January 2019
- |l1i cache=128 KiB5 KB (736 words) - 03:44, 19 August 2023
- |l1i cache=128 KiB5 KB (558 words) - 16:15, 13 December 2017
- *** Shrinkable from 512 KiB to 128 KiB (2-way) ...is [[competitively shared]] between threads. The branch buffer target has 128 entries (4-way by 32 sets). While [[unconditional jumps]] are not recorded38 KB (5,468 words) - 20:29, 23 May 2019
- *** Shrinkable from 512 KiB to 128 KiB (2-way) * Branch buffer target has 128 entries (4-way, 32 sets)7 KB (872 words) - 19:42, 30 November 2017
- * DTLB table size doubled (128 entries -> 256 entries)5 KB (568 words) - 19:40, 30 November 2017
- ** DIV is more than twice as fast as Airmont, 13 cycles for most divides, 128-bit/64-bit are ~42 cycles.7 KB (956 words) - 23:05, 23 March 2020
- |l1i cache=128 KiB4 KB (529 words) - 17:41, 27 March 2018
- |l1i cache=128 KiB5 KB (701 words) - 17:40, 27 March 2018
- |l1i cache=128 KiB4 KB (540 words) - 17:40, 27 March 2018
- |l1i cache=128 KiB5 KB (724 words) - 06:10, 2 December 2018
- |l1i cache=128 KiB4 KB (535 words) - 17:39, 27 March 2018
- |l1i cache=128 KiB4 KB (533 words) - 17:41, 27 March 2018
- * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM) * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM)13 KB (1,784 words) - 08:04, 6 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (593 words) - 02:17, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (593 words) - 02:18, 1 April 2019
- |max memory=128 GiB ...nm process]]. It operates at 2.2 GHz with a TDP of 35 W and supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (582 words) - 02:21, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (596 words) - 02:18, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:16, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.5 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:16, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (593 words) - 02:17, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.3 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:16, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.4 KB (596 words) - 02:17, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.4 KB (595 words) - 09:36, 14 May 2021
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.4 KB (595 words) - 02:16, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:18, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.4 KB (595 words) - 02:16, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:17, 1 April 2019
- |l4=128 MiB *** 128 MiB14 KB (1,891 words) - 14:37, 6 January 2022
- |l4=128 MB *** 128 MB27 KB (3,750 words) - 06:57, 18 November 2023
- ...rocess 16 nm which reflects those relaxed pitches. TSMC demonstrated their 128 Mebibit [[SRAM]] wafer from their 16 nm HKMG FinFET process at the 2014 IEE ! colspan="2" | TSMC 128 Mib SRAM demo 16 nm wafer4 KB (580 words) - 17:00, 26 March 2019
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (522 words) - 20:46, 4 October 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (537 words) - 15:01, 13 December 2019
- **** Increased to 168 entries (from 128) ***** 256-bit operations (from 128-bit)84 KB (13,075 words) - 00:54, 29 December 2020
- |side cache=128 MiB *** 64 MiB & 128 MiB [[eDRAM]]79 KB (11,922 words) - 06:46, 11 November 2022
- *** 64 MiB & 128 MiB [[eDRAM]] **** 128 entries; 8-way set associative38 KB (5,431 words) - 10:41, 8 April 2024
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (415 words) - 16:24, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (415 words) - 16:24, 13 December 2017
- |max memory=128 GiB | max memory = 128 GiB4 KB (564 words) - 14:29, 24 March 2019
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (710 words) - 16:24, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (710 words) - 03:49, 26 June 2018
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (573 words) - 16:24, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (558 words) - 23:13, 12 March 2019
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (544 words) - 16:24, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (542 words) - 16:24, 13 December 2017
- |l1 cache=128 KiB4 KB (649 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB4 KB (649 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB4 KB (654 words) - 17:22, 26 March 2018
- Samsung demonstrated their 128 Megabit [[SRAM]] wafer from their 10nm FinFET process. Samsung, which unlik ! colspan="2" | Samsung 128 Mib SRAM demo 10 nm wafer14 KB (1,903 words) - 06:52, 17 February 2023
- ...Hwasung-gun, Kyonggi Province. Line 10 was dedicated for the production of 128 MiB, 256 MiB and [[Rambus]] [[DRAM]]s on a 150 nm process. Line 10 opened i2 KB (238 words) - 02:56, 27 September 2020
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (485 words) - 00:29, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (620 words) - 00:27, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (490 words) - 00:29, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (489 words) - 16:26, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (609 words) - 00:29, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (484 words) - 16:26, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (490 words) - 00:29, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (608 words) - 16:26, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (506 words) - 00:29, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (620 words) - 00:24, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (490 words) - 00:29, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (624 words) - 00:27, 7 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (648 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (646 words) - 05:24, 14 July 2018
- ...] operating at 350 MHz with a turbo frequency of 1.1 GHz and incorporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR |l1i cache=128 KiB4 KB (654 words) - 16:27, 13 December 2017
- ...operating at 350 MHz with a turbo frequency of 1.05 GHz and incorporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR |l1i cache=128 KiB4 KB (654 words) - 16:27, 13 December 2017
- ...s]] operating at 350 MHz with a turbo frequency of 1 GHz and incorporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR |l1i cache=128 KiB4 KB (663 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (640 words) - 16:27, 13 December 2017
- ...ake's highest tier GPU incorporating 72 execution units as well as a large 128 MiB [[eDRAM]] of cache. The P580 GPU is found in high-end mobile workstatio4 KB (489 words) - 13:38, 9 July 2017
- |l1 cache=128 KiB4 KB (607 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (610 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (616 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (623 words) - 06:18, 5 November 2020
- |l1 cache=128 KiB4 KB (610 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (606 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (581 words) - 17:57, 28 August 2018
- |l1 cache=128 KiB4 KB (597 words) - 16:25, 13 December 2017
- * {{\|Riva 128}}3 KB (261 words) - 16:48, 20 March 2024
- |max memory=128 GiB ...4 nm process]]. It operates at 1.3 GHz with a TDP of 20 W supporting up to 128 GiB of dual-channel DDR4-1600 memory.4 KB (613 words) - 02:20, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.2 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (596 words) - 02:16, 1 April 2019
- |max memory=128 GiB ...el|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (596 words) - 02:16, 1 April 2019
- |l1 cache=128 KiB4 KB (613 words) - 17:58, 28 August 2018
- |l1 cache=128 KiB4 KB (613 words) - 17:58, 28 August 2018
- |l1 cache=128 KiB4 KB (613 words) - 17:58, 28 August 2018
- |l1 cache=128 KiB4 KB (613 words) - 17:58, 28 August 2018
- |l1 cache=128 KiB4 KB (616 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (609 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (618 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (612 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (611 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (615 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (615 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (613 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (613 words) - 02:11, 16 January 2019
- |l1 cache=128 KiB4 KB (613 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (609 words) - 16:16, 13 December 2017
- |l1 cache=128 KiB4 KB (606 words) - 16:16, 13 December 2017
- * '''Mem:''' Up to 128 GiB; DDR4 up to 3200 MT/s or DDR5 up to 5600 MT/s34 KB (4,663 words) - 20:38, 20 February 2023
- ...chitecture that has a [[datapath]] width or a highest [[operand]] width of 128 bits or 16 [[octet]]s. These architectures typically have a matching [[regi ...number of microarchitectures that introduced various extensions to handle 128-bit arithmetic in a more specialized way.593 bytes (81 words) - 09:51, 20 July 2018
- ** 128 Byte, dualport RAM or FIFO4 KB (492 words) - 00:37, 28 June 2016
- |l4=128 MiB *** 64 MiB & 128 MiB [[eDRAM]]30 KB (4,192 words) - 13:48, 10 December 2023
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (745 words) - 00:23, 26 March 2023
- |l1i cache=128 KiB |l1d cache=128 KiB2 KB (286 words) - 14:52, 26 March 2019
- |l1 cache=128 KiB4 KB (626 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (654 words) - 17:58, 28 August 2018
- |l1 cache=128 KiB4 KB (660 words) - 18:04, 28 August 2018
- |l1 cache=128 KiB4 KB (650 words) - 17:50, 13 January 2021
- |l1 cache=128 KiB4 KB (652 words) - 18:04, 28 August 2018
- |l1 cache=128 KiB5 KB (799 words) - 17:27, 17 February 2023
- ** 128 entry TLB4 KB (578 words) - 18:57, 22 May 2019
- ** Larger Retire Queue (192, up from 128) .... On the floating point side, there is a different scheduler to handle the 128-bit FP operations. Zen support all modern {{x86|extensions|x86 extensions}}79 KB (12,095 words) - 15:27, 9 June 2023
- | {{amd|Rome|l=core}} || Up to 64/128 || High-end server [[multiprocessors]] | {{amd|Castle Peak|l=core}} || Up to 64/128 || Workstation & enthusiasts market processors57 KB (8,701 words) - 22:11, 9 October 2022
- |l1i cache=128 KiB6 KB (633 words) - 16:25, 13 December 2017
- |l1i cache=128 KiB5 KB (584 words) - 18:02, 9 February 2019
- |l1i cache=128 KiB6 KB (642 words) - 16:25, 13 December 2017
- |l1i cache=128 KiB7 KB (837 words) - 23:15, 25 August 2019
- |l1 cache=128 KiB2 KB (343 words) - 03:48, 20 October 2018
- ...SC2|the previous}} PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.3 KB (349 words) - 12:41, 28 September 2019
- ...h was also released at the same time, the K6-2+ only had half the [[L2$]] (128 KB), but still operated at full core speed. Due to the processor shrink, th2 KB (341 words) - 04:25, 26 October 2018
- |l2 cache=128 KiB2 KB (299 words) - 06:06, 24 March 2023
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (674 words) - 19:57, 22 October 2019
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (694 words) - 23:04, 15 April 2019
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (699 words) - 11:45, 15 April 2019
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (665 words) - 12:47, 4 June 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (658 words) - 16:20, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (677 words) - 16:20, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (665 words) - 21:59, 13 September 2018
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (684 words) - 16:20, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (659 words) - 16:20, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (677 words) - 16:20, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (493 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (493 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (637 words) - 01:04, 24 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (637 words) - 01:04, 24 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (485 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (477 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (605 words) - 16:26, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (489 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (625 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (489 words) - 16:27, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (616 words) - 16:26, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (489 words) - 16:26, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (492 words) - 16:26, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (667 words) - 16:26, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (540 words) - 10:01, 1 November 2018
- |l1 cache=128 KiB5 KB (663 words) - 13:08, 28 March 2021
- |l1 cache=128 KiB4 KB (621 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (651 words) - 15:08, 24 December 2017
- ...den, Germany]]. The core implements an exclusive 256 [[KiB]] [[L2$]] and a 128 KiB [[L1$]]. As with all [[Socket A]] processors ({{decc|EV6}} system bus),11 KB (1,571 words) - 18:57, 17 November 2016
- |l1 cache=128 KiB5 KB (687 words) - 02:21, 16 January 2019
- |l1 cache=128 KiB4 KB (644 words) - 14:59, 24 December 2017
- |l1 cache=128 KiB5 KB (661 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB5 KB (662 words) - 06:02, 27 October 2018
- |l1 cache=128 KiB4 KB (655 words) - 16:26, 13 December 2017
- |l1 cache=128 KiB4 KB (655 words) - 15:07, 24 December 2017
- |l1 cache=128 KiB4 KB (638 words) - 13:29, 7 April 2018
- |l1 cache=128 KiB4 KB (636 words) - 13:30, 7 April 2018
- |l1 cache=128 KiB4 KB (655 words) - 13:30, 7 April 2018
- |l1 cache=128 KiB5 KB (685 words) - 16:18, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (542 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (538 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (542 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (500 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (508 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (508 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (508 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (508 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (508 words) - 15:20, 13 December 2017
- | die area = 128 mm² |l1 cache=128 KiB4 KB (508 words) - 15:20, 13 December 2017
- |l1 cache=128 KiB4 KB (494 words) - 15:20, 13 December 2017
- |l1 cache=128 KiB4 KB (492 words) - 15:20, 13 December 2017
- |l1 cache=128 KiB4 KB (493 words) - 15:20, 13 December 2017
- |l1 cache=128 KiB4 KB (494 words) - 15:20, 13 December 2017
- |l1 cache=128 KiB4 KB (492 words) - 15:20, 13 December 2017
- |l1 cache=128 KiB4 KB (494 words) - 15:20, 13 December 2017
- |l1 cache=128 KiB4 KB (488 words) - 15:20, 13 December 2017
- |l1 cache=128 KiB4 KB (488 words) - 15:20, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (493 words) - 16:15, 11 February 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (498 words) - 16:23, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (498 words) - 16:23, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (498 words) - 08:12, 20 June 2023
- |l1 cache=128 KiB5 KB (563 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB4 KB (558 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB5 KB (580 words) - 12:03, 26 March 2020
- |l1 cache=128 KiB5 KB (571 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB5 KB (560 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB5 KB (573 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB5 KB (571 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB5 KB (567 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB5 KB (569 words) - 16:23, 13 December 2017
- |l1 cache=128 KiB5 KB (558 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB5 KB (572 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB5 KB (575 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB5 KB (558 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB5 KB (575 words) - 07:19, 5 August 2019
- |l1 cache=128 KiB4 KB (556 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB5 KB (581 words) - 04:07, 31 March 2020
- |l1 cache=128 KiB5 KB (561 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB5 KB (584 words) - 10:47, 24 March 2019
- |l1 cache=128 KiB5 KB (568 words) - 03:00, 15 September 2019
- |l1 cache=128 KiB4 KB (556 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB5 KB (568 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB5 KB (563 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB5 KB (568 words) - 17:18, 26 November 2018
- |l1 cache=128 KiB4 KB (556 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB4 KB (548 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (537 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (538 words) - 11:34, 28 October 2020
- |l1 cache=128 KiB4 KB (543 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (555 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (536 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (553 words) - 10:07, 16 September 2021
- |l1 cache=128 KiB4 KB (546 words) - 16:17, 13 December 2017
- |l1 cache=128 KiB4 KB (533 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (533 words) - 23:15, 12 November 2020
- |l1 cache=128 KiB4 KB (533 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (533 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (527 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (527 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (530 words) - 16:16, 13 December 2017
- |l1 cache=128 KiB4 KB (532 words) - 16:16, 13 December 2017
- |l1 cache=128 KiB4 KB (528 words) - 16:16, 13 December 2017
- |l1 cache=128 KiB4 KB (527 words) - 16:16, 13 December 2017
- |l1 cache=128 KiB4 KB (532 words) - 16:16, 13 December 2017
- |l1 cache=128 KiB4 KB (527 words) - 16:16, 13 December 2017
- |l1 cache=128 KiB5 KB (570 words) - 16:22, 13 December 2017
- |l1 cache=128 KiB4 KB (559 words) - 16:19, 13 December 2017
- |l1 cache=128 KiB5 KB (570 words) - 16:22, 13 December 2017
- |l2=128 KiB - 2 MiB6 KB (758 words) - 13:01, 6 March 2022
- *** 128 B line locking and partitioning ...M]] controller with support for up to 16 GiB of single-channel 64-bit (and 128-bit for 8- and 16-core models) [[DDR1]]/[[DDR2]] up to 400 MHz for 5.96 GiB7 KB (870 words) - 19:38, 23 June 2017
- ...rocessors with up [[16 cores]]. These processors offer up to 16 [[GiB]] of 128-bit DDR2-800 ECC memory. Additionally these chips integrate multiple standa11 KB (1,489 words) - 09:25, 30 December 2020
- |l2 cache=128 KiB4 KB (465 words) - 16:10, 13 December 2017
- |l2 cache=128 KiB4 KB (465 words) - 16:10, 13 December 2017
- |l2 cache=128 KiB4 KB (465 words) - 16:10, 13 December 2017
- |l2 cache=128 KiB4 KB (449 words) - 16:10, 13 December 2017
- |l2 cache=128 KiB4 KB (449 words) - 16:10, 13 December 2017
- |l2 cache=128 KiB4 KB (449 words) - 16:10, 13 December 2017
- |l1i cache=128 KiB4 KB (435 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB4 KB (432 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB4 KB (432 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB4 KB (415 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB4 KB (412 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB4 KB (426 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB4 KB (412 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB4 KB (423 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB4 KB (423 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (432 words) - 16:11, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (432 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (412 words) - 16:11, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (423 words) - 16:11, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (423 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (396 words) - 16:13, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |l1i cache=128 KiB |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (419 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (396 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (410 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (410 words) - 16:12, 13 December 2017
- |width=128 bit4 KB (419 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (419 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (419 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (419 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (396 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (396 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (396 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (410 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (410 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (410 words) - 16:13, 13 December 2017
- |width=128 bit4 KB (410 words) - 16:13, 13 December 2017
- |l1d cache=128 KiB4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB4 KB (419 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB4 KB (398 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB4 KB (398 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB4 KB (398 words) - 16:12, 13 December 2017
- |l1d cache=128 KiB4 KB (398 words) - 16:12, 13 December 2017
- |l1 cache=128 KiB4 KB (647 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (646 words) - 07:22, 13 December 2018
- |l1 cache=128 KiB5 KB (687 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (604 words) - 13:42, 8 April 2018
- |l1 cache=128 KiB4 KB (604 words) - 13:42, 8 April 2018
- |l1 cache=128 KiB4 KB (636 words) - 16:18, 13 December 2017
- |l1 cache=128 KiB4 KB (595 words) - 13:42, 8 April 2018
- |l1 cache=128 KiB4 KB (587 words) - 16:15, 13 December 2017
- |l1 cache=128 KiB4 KB (581 words) - 10:08, 11 February 2019
- |l1 cache=128 KiB4 KB (642 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (642 words) - 16:25, 13 December 2017
- |l1 cache=128 KiB4 KB (612 words) - 08:31, 29 September 2019
- |l1 cache=128 KiB4 KB (626 words) - 18:04, 28 August 2018
- |l1 cache=128 KiB4 KB (649 words) - 18:04, 28 August 2018
- |l1 cache=128 KiB4 KB (640 words) - 16:20, 13 December 2017
- |l1 cache=128 KiB4 KB (641 words) - 14:22, 16 March 2018
- |l1 cache=128 KiB4 KB (640 words) - 16:20, 13 December 2017
- |l1 cache=128 KiB4 KB (640 words) - 07:01, 20 March 2019
- |l1 cache=128 KiB4 KB (642 words) - 13:35, 4 July 2022
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (636 words) - 00:28, 11 July 2019
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (619 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (629 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (640 words) - 13:42, 8 April 2018
- |l1 cache=128 KiB4 KB (647 words) - 16:23, 13 December 2017
- |l1 cache=128 KiB4 KB (647 words) - 16:23, 13 December 2017
- |l1 cache=128 KiB4 KB (654 words) - 17:06, 22 December 2017
- |l1 cache=128 KiB4 KB (647 words) - 23:30, 3 October 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (626 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (662 words) - 09:53, 14 May 2021
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (626 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (626 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (636 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (634 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (636 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (645 words) - 13:42, 8 April 2018
- The Execution Unit is composed of 7 threads. Each thread has 128 SIMD-8 32-bit registers in a General-Purpose Register File (GRF) and suppor29 KB (3,752 words) - 13:14, 19 April 2023
- ...|Iris Pro Graphics P555}} || 48 || GT3e || {{intel|Skylake H|H|l=core}} || 128 MiB ...l|Iris Pro Graphics 580}} || 72 || GT4e || {{intel|Skylake H|H|l=core}} || 128 MiB33 KB (4,255 words) - 17:41, 1 November 2018
- *** 128-byte lines (broken into four 32-byte sectors) *** 128-byte cache line with support for 64-byte sectors14 KB (1,905 words) - 23:38, 22 May 2020
- | l4 = 128 MiB2 KB (217 words) - 15:30, 3 September 2017
- ** 128-byte lines, interleaved ** 128-byte lines, 128 B interleaved6 KB (822 words) - 13:01, 19 May 2021
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (517 words) - 10:12, 24 October 2018
- |l1i cache=128 KiB |l1d cache=128 KiB3 KB (516 words) - 10:12, 24 October 2018
- ** ASIMD-128 ...with both units supporting FMA as well as two 64-bit FP operations or one 128-bit FP operation by combining two units.7 KB (940 words) - 00:12, 8 March 2021
- * '''Mem:''' Up to 128 GiB of dual-channel 3200 MT/s DDR4 memory15 KB (2,095 words) - 12:18, 2 October 2022
- * '''Mem:''' Up to 128 GiB of dual-channel 2666 MT/s DDR4 memory * '''Mem:''' Up to 128 GiB of dual-channel 3200 MT/s DDR4 memory14 KB (1,864 words) - 07:09, 7 October 2020
- |l1d cache=128 KiB3 KB (540 words) - 23:32, 25 March 2023
- |l3 cache=128 MiB |pcie lanes=1283 KB (563 words) - 11:06, 15 April 2020
- | {{amd|Milan|l=core}} || Up to 64/128 || High-end server [[multiprocessors]] | {{amd|Chagall|l=core}} || Up to 64/128 || Workstation & enthusiasts market processors15 KB (1,978 words) - 22:13, 6 April 2023
- ...up to 64 cores (and 128 threads) for a 2-way MP system. Those SoCs sports 128 PCIe lanes each, however, half of them are lost when in 2-way MP (leaving t * 128 PCIe lanes (in both single-way and dual-way multiprocessing)3 KB (450 words) - 13:49, 18 November 2018
- |l1d cache=128 KiB3 KB (528 words) - 23:32, 25 March 2023
- |l1 cache=128 KiB4 KB (418 words) - 16:31, 13 December 2017
- |l1 cache=128 KiB4 KB (428 words) - 16:31, 13 December 2017
- |l1 cache=128 KiB4 KB (440 words) - 16:31, 13 December 2017
- |l1 cache=128 KiB4 KB (461 words) - 16:31, 13 December 2017
- |l1 cache=128 KiB4 KB (455 words) - 16:31, 13 December 2017
- |l1 cache=128 KiB5 KB (591 words) - 16:31, 13 December 2017
- |l1 cache=128 KiB3 KB (337 words) - 16:31, 13 December 2017
- | max memory = 128 GB |max mem=128 GiB4 KB (473 words) - 09:26, 3 December 2019
- |l1 cache=128 KiB4 KB (678 words) - 18:04, 28 August 2018
- |l1d cache=128 KiB3 KB (508 words) - 23:31, 25 March 2023
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (663 words) - 14:54, 12 January 2020
- ...timestamp=2017-10-14 17:03:24-0400|chip_count=4|core_count=64|copies_count=128|vendor=HPE|system=ProLiant DL580 Gen10 (2.10 GHz, Intel Xeon Gold 6130)|SPE ...timestamp=2017-10-14 06:15:36-0400|chip_count=4|core_count=64|copies_count=128|vendor=HPE|system=ProLiant DL580 Gen10 (2.10 GHz, Intel Xeon Gold 6130)|SPE9 KB (1,276 words) - 01:20, 29 December 2019
- ...timestamp=2017-10-19 14:32:28-0400|chip_count=4|core_count=64|copies_count=128|vendor=Dell Inc.|system=PowerEdge R940 (Intel Xeon Platinum 8153, 2.00 GHz) ...timestamp=2017-10-20 02:06:06-0400|chip_count=4|core_count=64|copies_count=128|vendor=Dell Inc.|system=PowerEdge R940 (Intel Xeon Platinum 8153, 2.00 GHz)9 KB (1,264 words) - 02:37, 29 December 2019
- |l1i cache=128 KiB |l1d cache=128 KiB9 KB (1,325 words) - 14:20, 8 May 2019
- ...B]] of memory per socket (for up to 4 TiB in 2-way MP). Each processor has 128 [[PCIe]] lanes and non-P models also support two-way multiprocessing utiliz19 KB (2,580 words) - 02:46, 23 November 2022
- ...p to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs support 128 PCIe lanes each. When in a two-socket configuration, a total of 160 PCIe la * 128 PCIe lanes (in both single-way and dual-way multiprocessing)6 KB (828 words) - 16:47, 15 April 2020
- ...ay multiprocessing as well as 2-way multithreading with up to 64 cores and 128 threads per processor. AMD claims up to 15% better performance per cost and ...pported by all EPYC 7003 <abbr title="Stock Keeping Unit">SKU</abbr>s with 128 MiB L3 cache or less, none having only two <abbr title="Core Complex Die">C19 KB (2,734 words) - 01:26, 31 May 2021
- ...e Lake U processors use {{intel|BGA-1356|Socket BGA-1528}} and incorporate 128 MiB of side cache. ** 128 MiB of eDRAM side cache4 KB (553 words) - 23:05, 12 May 2020
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (787 words) - 02:57, 20 July 2023
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (787 words) - 16:38, 23 November 2018
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (787 words) - 05:58, 9 October 2023
- * Symmetric crypto: AES (128 to 256 & ECB, CBC, CTR/XTS modes), DES/3DES (ECB & CBC), RC46 KB (683 words) - 16:31, 13 December 2017
- * Symmetric crypto: AES (128 to 256 & ECB, CBC, CTR/XTS modes), DES/3DES (ECB & CBC), RC46 KB (666 words) - 16:31, 13 December 2017
- * Symmetric crypto: AES (128 to 256 & ECB, CBC, CTR/XTS modes), DES/3DES (ECB & CBC), RC46 KB (681 words) - 17:03, 24 January 2018
- * '''Mem:''' Up to 128 GiB of quad-channel DDR4 at rates up 2666 MT/s9 KB (1,197 words) - 02:30, 6 April 2024
- ** Up to 128 GiB3 KB (470 words) - 10:12, 24 October 2018
- * '''Mem:''' Up to 128 GiB of quad-channel DDR4-2666 * '''Mem:''' Up to 128 GiB of quad-channel DDR4-26668 KB (1,188 words) - 23:47, 11 October 2018
- |max memory=128 GiB ...d a {{intel|Turbo Boost}} frequency of 4 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2400 memory.4 KB (601 words) - 17:13, 13 June 2019
- |max memory=128 GiB ...a {{intel|Turbo Boost}} frequency of 4.3 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.4 KB (613 words) - 07:01, 27 February 2019
- |max memory=128 GiB ...a {{intel|Turbo Boost}} frequency of 4.3 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.4 KB (617 words) - 10:13, 4 April 2019
- |max memory=128 GiB ...a {{intel|Turbo Boost}} frequency of 4.3 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.4 KB (614 words) - 10:17, 24 October 2018
- |max memory=128 GiB ...a {{intel|Turbo Boost}} frequency of 4.3 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.4 KB (606 words) - 14:34, 10 June 2020
- |max memory=128 GiB ...a {{intel|Turbo Boost}} frequency of 4.2 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.4 KB (608 words) - 15:46, 25 January 2019
- ...ors (i.e., those with {{intel|Iris Pro Graphics 580}}) incorporate a large 128 MiB of side cache on-package.5 KB (630 words) - 02:08, 16 January 2019
- ...doesn't have Unicode code points above 255, to avoid having Unicode points 128-255 encoded to 2-byte pairs, the text must be fed to $sha1 as a binary vari ...a1 can corrupt the contents of the &binvar it is hashing. If the length is 128+, and the file is split into 64-byte chunks, the 1st chunk is never affecte5 KB (914 words) - 23:42, 21 October 2022
- ...different states which could have returned the latest 64-bit value, and 2^128 possible states returning that exact combo of 64bit values. This RNG should7 KB (1,201 words) - 09:57, 11 February 2024
- To store the 128 hexadecimal digits of the sha512 hash digest in fewer digits, you can't use shortened 128 d8022f2060ad6efd297ab73dcc5355c9b214054b0d1776a136a669d26a7d3b14f73aa0d0ebf7 KB (1,020 words) - 06:40, 13 November 2022
- ...doesn't have Unicode code points above 255, to avoid having Unicode points 128-255 encoded to 2-byte pairs, the text must be fed to $crc as a binary varia4 KB (671 words) - 07:25, 21 September 2017
- ** 64/128-bit data bus4 KB (527 words) - 02:09, 4 August 2017
- |l1 cache=128 KiB4 KB (653 words) - 13:36, 16 February 2024
- |l1 cache=128 KiB4 KB (643 words) - 13:29, 7 April 2018
- |l1 cache=128 KiB4 KB (609 words) - 16:18, 13 December 2017
- |l1i cache=128 KiB |l1d cache=128 KiB5 KB (702 words) - 13:42, 8 April 2018
- |l1i cache=128 KiB |l1d cache=128 KiB4 KB (626 words) - 13:42, 8 April 2018
- The EPYC 7351P has 128 Gen 3 PCIe lanes. | pcie lanes = 1283 KB (531 words) - 12:24, 18 March 2023
- The EPYC 7401P has 128 Gen 3 PCIe lanes. | pcie lanes = 1284 KB (557 words) - 12:26, 18 March 2023
- The EPYC 7551P has 128 Gen 3 PCIe lanes. | pcie lanes = 1284 KB (563 words) - 12:30, 18 March 2023
- ...on, half of the lanes are used for inter-processor communication, so again 128 lanes are available for expansions. | pcie lanes = 1285 KB (694 words) - 12:30, 18 March 2023