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CN5830-600 EXP - Cavium
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Cavium CN5830-600 EXP
octeon plus chip.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5830-600 EXP
Part NumberCN5830-600BG1521-EXP
MarketNetwork
IntroductionOctober 9, 2006 (announced)
February, 2007 (launched)
General Specs
FamilyOCTEON Plus
SeriesCN58xx
Frequency600 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max CPUs1 (Uniprocessor)
Electrical
Power dissipation15 W
Packaging
PackageFCBGA-1521 (BGA)
Ball Count1521
InterconnectBGA-1521

CN5830-600 EXP is a 64-bit quad-core MIPS network microprocessor designed by Cavium and introduced in 2007. This processor, which incorporates four cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as RegEx, compression/decompression, and TCP acceleration.


Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
0.188 MiB
196,608 B
1.831055e-4 GiB
L1I$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB64-way set associative 
L1D$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
4x16 KiB64-way set associative 

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
Bandwidth
Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2

GP I/OYes

Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
RegEx
RegExYes
Features32 Engines
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes

Block diagram[edit]

octeon plus cn58xx.png

Datasheet[edit]

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5830-600 EXP - Cavium#package +
base frequency600 MHz (0.6 GHz, 600,000 kHz) +
core count4 +
designerCavium +
familyOCTEON Plus +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus/cn5830-600bg1521-exp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.188 MiB (192 KiB, 196,608 B, 1.831055e-4 GiB) +
l1d$ description64-way set associative +
l1d$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
l1i$ description64-way set associative +
l1i$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateFebruary 2007 +
main imageFile:octeon plus chip.png +
manufacturerTSMC +
market segmentNetwork +
max cpu count1 +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN5830-600 EXP +
nameCavium CN5830-600 EXP +
packageFCBGA-1521 +
part numberCN5830-600BG1521-EXP +
power dissipation15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN58xx +
supported memory typeDDR2-800 +
technologyCMOS +
thread count4 +
word size64 bit (8 octets, 16 nibbles) +