|Cavium CN3850-400 EXP|
|Model Number||CN3850-400 EXP|
|Introduction||August 22, 2005 (announced)|
August 22, 2005 (launched)
|Word Size||64 bit|
|Max Memory||16 GiB|
|Max SMP||1-Way (Uniprocessor)|
The CN3850-400 EXP is a 64-bit dodeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU
by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.
The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.
Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.
Note: All units are in kibibytes
|12x32 KiB||64-way set associative|| |
|12x8 KiB||64-way set associative||Write-through|
| || ||1x1 MiB||8-way set associative|| |
[Edit/Modify Memory Info]
Integrated Memory Controller
|Max Mem||16 GiB|
|Max Bandwidth||11.92 GiB/s|
Single 11.92 GiB/s