|Cavium CN5850-600 SCP|
|Model Number||CN5850-600 SCP|
|Introduction||October 9, 2006 (announced)|
February, 2007 (launched)
|Word Size||64 bit|
|Max CPUs||1 (Uniprocessor)|
CN5850-600 SCP is a 64-bit dodeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU
by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.
The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.
Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.
Note: All units are in kibibytes
|12x32 KiB||64-way set associative|| |
|12x16 KiB||64-way set associative|| |
| || ||1x2 MiB||8-way set associative|| |
[Edit/Modify Memory Info]
Integrated Memory Controller
|Max Bandwidth||11.92 GiB/s|
Single 11.92 GiB/s
[Edit/Modify Accelerators Info]
|Types||DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI|