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Godson-2C - Loongson
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Godson-2C
godson-2c.jpg
Godson-2C chip
General Info
DesignerLoongson
ManufacturerSMICS
Model Number2C
Part NumberDXP100
MarketDesktop
Introduction2004 (announced)
September 28, 2004 (launched)
General Specs
FamilyGodson 2
SeriesGodson 2
Frequency500 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitectureGS464
Core NameGS464
Process180 nm
Transistors13,500,000
TechnologyCMOS
Die41.54 mm²
6,200 µm × 6,700 µm
Word Size64 bit
Cores1
Threads1
Max CPUs1 (Uniprocessor)
Electrical
Power dissipation5 W

Godson-2C (龙芯2C) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late 2004, the Godson-2C operates at up to 500 MHz consuming 3-5W. This chip was manufactured on SMICS' 0.18 µm process. This chip reached tapeout on June 8, 2004.

The Godson-2C provides roughly three times the performance of 2B. The 2C has twice the cache and almost twice the frequency as the 2B, along with an improved branch predictor.

Loongson has claimed the Godson-2C has reached the performance level of 500-800 MHz PIII based on their SPECint2000 scores.

Cache[edit]

Main article: GS464 § Cache

This chip was typically combined with 1 MiB - 8 MiB L2 cache off-die (on the motherboard).

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
L1I$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB4-way set associative 
L1D$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB4-way set associative 

References[edit]

  • Hu, Wei-Wu, and Jian Wang. "Making effective decisions in computer architects’ real-world: Lessons and experiences with Godson-2 processor designs." Journal of Computer Science and Technology 23.4 (2008): 620-632.
Facts about "Godson-2C - Loongson"
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count1 +
core nameGS464 +
designerLoongson +
die area41.54 mm² (0.0644 in², 0.415 cm², 41,540,000 µm²) +
die length6.2 mm (0.62 cm, 0.244 in, 6,200 µm) +
die width6.7 mm (0.67 cm, 0.264 in, 6,700 µm) +
familyGodson 2 +
first announced2004 +
first launchedSeptember 28, 2004 +
full page nameloongson/godson 2/2c +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l1d$ description4-way set associative +
l1d$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldateSeptember 28, 2004 +
main imageFile:godson-2c.jpg +
main image captionGodson-2C chip +
manufacturerSMICS +
market segmentDesktop +
max cpu count1 +
microarchitectureGS464 +
model number2C +
nameGodson-2C +
part numberDXP100 +
power dissipation5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
process180 nm (0.18 μm, 1.8e-4 mm) +
seriesGodson 2 +
technologyCMOS +
thread count1 +
transistor count13,500,000 +
word size64 bit (8 octets, 16 nibbles) +