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CN5860-1000 SCP - Cavium
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Cavium CN5860-1000 SCP
octeon plus chip.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5860-1000 SCP
Part NumberCN5860-1000BG1521-SCP
MarketNetwork
IntroductionOctober 9, 2006 (announced)
February, 2007 (launched)
Release Price$987
General Specs
FamilyOCTEON Plus
SeriesCN58xx
Frequency1,000 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores16
Threads16
Max CPUs1 (Uniprocessor)
Electrical
Power dissipation40 W
Packaging
PackageFCBGA-1521 (BGA)
Ball Count1521
InterconnectBGA-1521

CN5860-1000 SCP is a 64-bit hexadeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.


Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
0.75 MiB
786,432 B
7.324219e-4 GiB
L1I$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
16x32 KiB64-way set associative 
L1D$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
16x16 KiB64-way set associative 

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
Bandwidth
Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2

GP I/OYes

Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI
Networking
TCPYes
QoSYes

Block diagram[edit]

octeon plus cn58xx.png

Datasheet[edit]

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5860-1000 SCP - Cavium#package +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
core count16 +
designerCavium +
familyOCTEON Plus +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus/cn5860-1000bg1521-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
l1d$ description64-way set associative +
l1d$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l1i$ description64-way set associative +
l1i$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateFebruary 2007 +
main imageFile:octeon plus chip.png +
manufacturerTSMC +
market segmentNetwork +
max cpu count1 +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN5860-1000 SCP +
nameCavium CN5860-1000 SCP +
packageFCBGA-1521 +
part numberCN5860-1000BG1521-SCP +
power dissipation40 W (40,000 mW, 0.0536 hp, 0.04 kW) +
process90 nm (0.09 μm, 9.0e-5 mm) +
release price$ 987.00 (€ 888.30, £ 799.47, ¥ 101,986.71) +
seriesCN58xx +
supported memory typeDDR2-800 +
technologyCMOS +
thread count16 +
word size64 bit (8 octets, 16 nibbles) +